Design Verification Intern — SystemVerilog & UVM

Analog Devices, Inc.; City of Edinburgh; On-site; GBP 17,000 - 25,000; Full time

Benefits offered by this job

Mentorship

Exposure to modern EDA tools

Opportunity for full-time conversion

Job summary

Analog Devices, Inc. in the United Kingdom is seeking a motivated Design Verification Intern to work with the CSS DV team on IP and subsystem validation for high-performance semiconductor products.

You will gain hands-on experience with SystemVerilog-based verification, simulations, testbench development, and functional coverage in a collaborative environment. The role targets students at bachelor’s, master’s, or PhD level in Electrical or Computer Engineering, offering mentorship, exposure to

Qualifications

• Strong understanding of digital logic design
• Coursework or practical exposure to Verilog/System Verilog or VHDL RTL design principles
• Familiarity with scripting languages (Python, Perl, Tcl, Bash)
• Experience with simulation workflows or testbench development
• Excellent communication and collaborative problem-solving abilities

Responsibilities

• Assist in developing and executing verification plans for digital IP blocks and subsystems.
• Develop, enhance, and maintain testbench components using System Verilog, UVM, or similar methodologies.
• Run simulations, analyze results, identify failures, and help debug issues.
• Create directed and constrained-random tests to validate functionality and corner cases.
• Perform functional, code, and assertion coverage reporting, review, and tracking.

Skills

Digital logic design

SystemVerilog/VHDL RTL design

Simulation workflows

Scripting languages

Communication skills

Education

Bachelor’s / Master’s / PhD in Electrical Engineering or related

Tools

Xcelium

Job description

Analog Devices, Inc. in the United Kingdom is seeking a motivated Design Verification Intern to work with the CSS DV team on IP and subsystem validation for high-performance semiconductor products.

You will gain hands-on experience with SystemVerilog-based verification, simulations, testbench development, and functional coverage in a collaborative environment. The role targets students at bachelor’s, master’s, or PhD level in Electrical or Computer Engineering, offering mentorship, exposure to