Design Verification Engineer

JR United Kingdom; Preston; On-site; GBP 40,000 - 70,000; Full time

Job summary

A leading technology firm in the United Kingdom is seeking a Design Verification Engineer for their Preston location. The ideal candidate will verify CPU connectivity to IP blocks and engage in comprehensive test planning, development, and execution. The role requires proficiency in UVM and various verification methodologies as part of ensuring design efficiency and reliability.

Qualifications

• Experience with CPU connectivity verification.
• Proficient in writing test plans and using verification methodologies.
• Familiarity with UVM and formal verification techniques.

Responsibilities

• Verify CPU connectivity to IP blocks and complete functional verification.
• Write test plans and develop test methodologies.
• Run regressions and debug test failures.

Skills

Verification techniques

Debugging

Test plan writing

Regressions

Code coverage analysis

Design checks

UVM

Verilog/SystemVerilog

Education

Bachelor's degree in Engineering or related field

Job description

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Design Verification Engineer, Preston, Lancashire

Client: ALOIS Solutions

Location: Preston, Lancashire, United Kingdom

Job Category: Other

EU work permit required: Yes

Job Views:

1

Posted:

31.05.2025

Expiry Date:

15.07.2025

Job Description:

• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)
• The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification, and closing coverage for all the agreed design blocks in the SoCs/Subsystems
• Run regressions, debug test failures, and file bug reports as needed
• Develop tests to meet functional coverage and code coverage requirements based on analysis of coverage gaps
• Provide verification reports to show all implemented tests passing on the RTL
• Methodologies will include design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based testcases