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Design Verification Engineer

JR United Kingdom

Kingston upon Hull

On-site

GBP 40,000 - 60,000

Full time

4 days ago
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Job summary

A leading company is seeking a Design Verification Engineer in Kingston upon Hull. This role focuses on verifying CPU connectivity and involves writing test plans, using various methodologies to ensure code coverage, and debugging failures alongside developing tests based on gap analyses. Ideal candidates will have strong experience in both design verification and utilizing related tools to validate subsystem functionalities.

Qualifications

  • Experience in CPU connectivity verification.
  • Proficient in developing test benches and defining test methodologies.
  • Knowledge of UVM and formal verification techniques.

Responsibilities

  • Verify CPU connectivity to IP blocks using ASM boot and C code.
  • Write test plans and complete functional verification.
  • Provide verification reports demonstrating all tests passing.

Skills

Verification methodologies
Test case writing
Debugging
Simulation

Tools

Verilog/SystemVerilog
GNU toolchain

Job description

Design Verification Engineer, Kingston upon Hull, East Yorkshire

Client:

ALOIS Solutions

Location:

Kingston upon Hull, East Yorkshire, United Kingdom

Job Category:

Other

EU work permit required:

Yes

Job Views:

1

Posted:

31.05.2025

Expiry Date:

15.07.2025

Job Description:
  • Verify CPU connectivity to IP blocks using ASM boot, C code, and GNU toolchain.
  • Write test plans, define test methodologies, develop test benches, write test cases, and complete functional verification and coverage closure for all design blocks in the SoCs/Subsystems.
  • Run regressions, debug test failures, and file bug reports as needed.
  • Develop tests to meet functional and code coverage requirements based on coverage gap analysis.
  • Provide verification reports demonstrating all tests passing on RTL.
  • Utilize verification methodologies including design checks, simulation, emulation, UVM, formal verification, and testbenches in Verilog/SystemVerilog and C.
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