Debug Validation Engineer — Multiple Levels

Linuxcareers; Bristol; On-site; GBP 60,000 - 80,000; Full time

Benefits offered by this job

Private medical insurance

Generous annual leave policy

Pension (matched up to 5%)

Employee assistance programme

Job summary

Linuxcareers is looking for a Debug Validation Engineer in the UK to lead post-silicon debug and validation of next-generation AI compute silicon. This role involves collaboration across hardware, firmware, and software teams to solve complex issues effectively.

The ideal candidate will have strong experience in bare metal environments and post-silicon validation processes, along with excellent programming skills, especially in Python. Competitive salary and various benefits including private medical insurance and generous leave policies are offered.

Qualifications

• Strong experience in bare metal environments and post-silicon validation processes for digital ASICs.
• Expertise in debug infrastructure and methodologies.
• Outstanding communication skills.

Responsibilities

• Lead post-silicon debugging and validation efforts for AI compute silicon.
• Analyze and address complex silicon, firmware, and software problems.
• Develop and improve automated debug and validation infrastructure.

Skills

Post-silicon validation processes

Debug infrastructure

Python programming

C programming

Linux experience

Analytical skills

Job description

Graphcore is building AI compute semiconductor and software technology as part of the SoftBank Group. This Debug Validation Engineer role reports to the Senior Director of Post Silicon Validation and leads post-silicon debug and validation activities for next-generation AI compute silicon and systems, combining deep technical debugging expertise with cross‑functional collaboration across hardware, firmware, software, and systems teams.

What You’ll Do

• Lead post-silicon debugging and validation efforts for AI compute silicon and platform technologies across multiple projects
• Analyze and address complex silicon, firmware, software, and system‑level problems during bring‑up, characterization, and validation phases
• Debug CPU, memory, interconnect, and high‑speed I/O subsystems under functional, stress, and workload conditions
• Develop and improve automated debug, regression, and validation infrastructure using Python and related technologies
• Analyze logs, traces, telemetry, and hardware data to isolate and characterize system failures and performance issues
• Develop structured debug methodologies and failure analysis processes to improve issue resolution efficiency
• Collaborate closely with architecture, RTL, firmware, software, and systems engineering teams to determine root causes and implement corrective measures
• Support silicon readiness reviews and contribute to product quality and release decisions

What You Need

• Strong experience in bare metal environments and post-silicon validation processes applied in digital ASIC environments
• Strong understanding of SoC and platform architectures
• Expertise in debug infrastructure and post‑silicon debug methodologies
• Strong programming skills in Python, C, or debug scripting languages such as CMM
• Strong Linux and Python experience
• Deep knowledge of scan, DFT, JTAG, and trace infrastructure
• Strong debug skills including fault tree analysis, failure isolation, fishbone methodologies, and system‑level debug techniques
• Outstanding communication skills and ability to collaborate effectively to solve complex problems
• Excellent problem‑solving, analytical, and diagnostic skills
• Capability to operate autonomously on technically intricate debug and validation tasks spanning hardware, firmware, and software

Nice to Have

• Understanding of DFT flows from insertion through post-silicon validation
• Experience developing tooling for parsing and analyzing debug data, including scan dump parsing
• Driver-level experience with PCIe, Ethernet, Memory technologies (LPDDR, DDR, HBM), or Peripheral interfaces (I2C, I3C, SPI)
• Experience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB, and STM
• Strong understanding of mixed‑signal components like PLLs and high‑speed PHYs
• Experience with Arm CPU architectures, system IP, and associated debug tooling
• Experience with AMBA protocols
• Understanding of ML applications and associated workloads
• Experience in characterization, failure analysis, test development, and statistical analysis

Competitive salary, flexible working, generous annual leave policy, private medical insurance and health cash plan, dental plan, pension (matched up to 5%), life assurance and income protection, generous parental leave policy, employee assistance programme including health and mental wellbeing support