[CONTRACT] SoC Verification Engineer

microTECH Global Limited; London; Remote; GBP 50,000 - 90,000; Full time

Job summary

An innovative firm is seeking a SoC Verification Engineer to join their dynamic team. This role involves deploying cutting-edge verification methodologies such as UVM and formal verification, developing robust testbenches, and collaborating closely with design teams to ensure the highest quality in complex SoC designs. The ideal candidate will have a strong background in SystemVerilog and experience with power-aware verification techniques. This is a fantastic opportunity to contribute to exciting projects in a fast-paced environment, where your skills will play a crucial role in advancing technology. If you are passionate about design verification and eager to make an impact, this position is perfect for you.

Qualifications

• Experience in design and verification on SoCs using industry standard tools.
• Proficient in developing unit and subsystem level test benches.

Responsibilities

• Deploying Verification Methodologies such as UVM and Formal Verification.
• Developing Testbenches and Verification Components like UVCs and C models.

Skills

SoC Verification

UVM Methodology

SystemVerilog

Python Automation

Debugging Skills

Analytical Skills

Education

Degree in Electrical Engineering or related field

Tools

System Verilog

C/C++

TCL/Perl/shell-scripting

Job description

Job Description

Job title: SoC Verification Engineer
Location: UK/Remote
Contract: Contract
Start: ASAP
Duration: 6 months
IR35: Inside

For our client, we are looking for a SoC Verification Engineer. Candidates must be based in the UK, although the work can be performed remotely.

Job Responsibilities

1. Deploying Verification Methodologies such as UVM and Formal Verification
2. Developing Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments
3. Test plan development based on Design documents and interaction with design/systems engineers
4. Writing and debugging SystemVerilog assertions
5. Analysing coverage data and working with Design teams to address coverage holes
6. Develop/augment framework for running regressions
7. Running/Debugging Power aware simulations (UPF)
8. Debugging regression failures with design/Systems teams
9. Python/Perl automation for improving workflows and team efficiency
10. Supporting software and other teams with debug
11. Documentation

Candidate Requirements

1. Experience in design and verification on SoCs and SoC Methodologies for verifying complex units on SoC using industry standard tools and technologies
2. Proficient in developing unit and subsystem level test benches using SV/UVM methodology
3. Constrained random and Metrics driven verification
4. Experienced with C model integration and scoreboarding
5. FW code integration verification
6. Experience with AMBA protocols and BUS interconnect functional and formal verification along with coverage closure
7. Experience with power aware verification and clock domain crossing verification
8. Experience with debugging test failures
9. Strong knowledge of verification planning, coverage analysis, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog
10. Experience with Verilog, C/C++, System C, TCL/Perl/shell-scripting
11. Strong analytical skills and ability to work in a dynamic and fast paced team environment