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ASIC Design Lead

JR United Kingdom

Plymouth

On-site

GBP 70,000 - 100,000

Full time

6 days ago
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Job summary

A leading company in semiconductor design is seeking an experienced ASIC Design Lead who will take ownership of IP and SoC-level design. This hands-on leadership role involves defining ASIC plans, driving functional coverage, and mentoring junior engineers. Ideal candidates will have significant digital design experience and be motivated by the challenges of building innovative technologies in a dynamic start-up environment.

Qualifications

  • 6+ years in digital Design with leadership experience.
  • Experience with FPGA technologies.
  • Familiarity with RISC-V or AI/GPU architectures.

Responsibilities

  • Define and execute ASIC plans for IP/SoC designs.
  • Drive functional coverage, assertions, and bug resolution.
  • Mentor junior engineers and guide verification best practices.

Skills

Problem-solving
Communication

Tools

FPGA
RISC-V
AI/GPU Architectures

Job description

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We are seeking an experienced ASIC Design Lead, to take ownership of IP and SoC-level design for next-generation semiconductor designs. This role offers the chance to lead a small team, shape verification strategy, and contribute to cutting-edge projects in a fast-paced, collaborative environment.

About the role:

As the ASIC Design Lead, you will be responsible for driving the development and execution of strategies for complex digital IP and SoCs.

This is a hands-on and leadership role suited to someone passionate, motivated by the challenges of building something from the ground up in a start-up environment.

What you will be doing:

  • Define and execute ASIC plans for IP/SoC designs
  • Drive functional coverage, assertions, and bug resolution
  • Collaborate with design, architecture, and software teams
  • Mentor junior engineers and guide verification best practices

Requirements:

  • 6+ years in digital Design, with leadership experience
  • Experience FPGA
  • Excellent problem-solving and communication skills
  • Familiarity with RISC-V or AI/GPU architectures

If you could be interested, please get in touch with me on the details below.

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