ASIC Architect

Quantum; Oxford; On-site; GBP 70,000 - 90,000; Full time

Job summary

A leading technology firm in the UK is seeking an experienced individual to lead the ASIC strategy for their cutting-edge probabilistic computing platform. This role involves overseeing the design lifecycle, managing vendor relationships, and collaborating with cross-functional teams to ensure high-performance integration with other processing units. Ideal candidates will have a strong background in system architecture, ASIC design, and excellent leadership skills. This is a unique opportunity to be at the forefront of innovation in computing.

Qualifications

• Strong understanding of system architecture and interface protocols.
• Proven track record managing ASIC projects from concept to production.
• Knowledge of low-power design techniques and high-speed interfaces.

Responsibilities

• Define and execute ASIC strategy and architecture.
• Oversee ASIC design lifecycle: specification, RTL design, verification.
• Manage relationships with semiconductor foundries and packaging vendors.

Skills

Assessment of ASIC vs FPGA vs GPU trade-offs

Communication and leadership skills

Job description

Role Summary

We are seeking an experienced candidate to lead the miniaturisation of our cutting‑edge probabilistic computing platform. This role is pivotal in defining and executing the ASIC strategy, ensuring optimal integration with other processing units such as FPGAs and GPUs. You will work closely with hardware engineers, algorithm designers and fabrication partners to deliver a high‑performance, cost‑effective solution.

Responsibilities

• ASIC strategy & architecture
  • Assess system components to determine which should be implemented as ASIC versus FPGA or GPU.
  • Define ASIC architecture in alignment with overall system requirements, including interfaces and memory hierarchy.
  • Evaluate trade‑offs between different processing units (ASIC, FPGA, GPU, SoC) for performance, power and scalability.
• Architectural planning
  • Define and own high‑level system architecture, refining requirements into functional, logical and physical architectures, interfaces and constraints.
  • Lead partitioning decisions (analogue vs digital domain, as well as core compute, memory and IO subsystems, chiplet selection, placement and interconnect strategy).
  • Oversee internal and third‑party IP for design blocks, chiplets, PDKs, chip‑to‑chip and die‑to‑die interfaces.
  • Drive top‑level floor planning.
  • Direct functional simulations and co‑simulation across multiple domains.
• Design & development
  • Oversee ASIC design lifecycle: specification, RTL design, verification and physical implementation.
  • Ensure compatibility with system‑level interfaces and integration requirements.
• Fabrication & packaging
  • Manage relationships with semiconductor foundries and packaging vendors.
  • Coordinate fabrication, packaging and testing processes to meet performance and reliability targets.
• Integration & validation
  • Lead integration of ASIC components into the broader computing platform.
  • Collaborate with software and hardware teams to validate functionality and optimise performance.
• Project management
  • Define milestones, budgets and resource allocation for the ASIC workstream.
  • Report progress and risks to senior leadership.

Technical expertise

• Strong understanding of system architecture, memory requirements and interface protocols.
• Knowledge of ASIC design flow, including synthesis, place‑and‑route and verification.
• Familiarity with FPGA and GPU architectures and their advantages.

Experience

• Proven track record managing ASIC projects from concept to production, including fabrication and packaging.
• Experience in heterogeneous computing systems and hardware‑software co‑design.

Skills

• Ability to assess trade‑offs between ASIC, FPGA and GPU implementations.
• Excellent communication and leadership skills for cross‑functional collaboration.

Preferred qualifications

• Experience with probabilistic or unconventional computing architectures.
• Familiarity with advanced packaging technologies (e.g., chiplets, 2.5D/3D integration).
• Knowledge of low‑power design techniques and high‑speed interfaces.

About the role

You’ll be at the forefront of next‑generation computing, shaping a platform that redefines performance and efficiency. This is an opportunity to lead innovation in a rapidly evolving field.