Real-Time Budget Planner

Hashlist; Toulouse; Híbrido; EUR 86.000 - 111.000; A tiempo parcial

Descripción de la vacante

Hashlist is seeking a freelance, hourly embedded systems engineer to build a benchmark environment around real-time controllers (ECU, motor or flight control units) in a hybrid France-based setup.

You will assemble task sets, source code, manuals, RTOS configs, and timing traces; configure cross-compilers, QEMU or IS simulators, trace tools, Python, and planning tools; and produce answer.json with WCET bounds, core/priority, and memory layout.

Formación

• Hands-on experience with real-time embedded systems (ECU/controller)
• Strong WCET and response-time analysis and schedulability skills
• Experience with RTOS configuration, task priorities and multicore assignments
• Proficient with cross-compilers, QEMU or IS simulators, and trace tools

Responsabilidades

• Build a benchmark environment around a real-time system (ECU, controller, flight or motor control unit).
• Include the task set, source code, MCU/SoC reference manuals and datasheets, RTOS configuration, linker map, timing traces and deadlines.
• Set up the tools needed—cross-compiler, QEMU or an instruction set simulator, trace tools, Python, PDF tools, and a schedulability analysis tool.
• Write five or more tasks, each built on timing or memory decisions, with WCET bounds and core/priority arrangements.
• Frame each task so the model produces an answer.json with WCET per routine, core/priority, and memory layout.
• Hide the deciding load inside traces (ISR/DMA bursts, bus/cache interference) and implement a hidden marking script to check bounds and deadlines.
• Provide both a scoring (1.0) and a naive answer (below 0.3), aiming to challenge frontier models.

Conocimientos

Real-time embedded systems

WCET analysis

Response-time analysis

Schedulability

Python

Cross-compiler usage

QEMU/instruction set simulator

Trace analysis

Herramientas

Cross-compiler

QEMU

Instruction set simulator

Trace tools

Python

PDF tools

Schedulability analysis tool

Descripción del empleo

• Location: France
• Working model: Hybrid
• Employment type: Freelance – hourly rate: $70–90 (paid per accepted task)
• Build a benchmark environment around a real-time system you have worked on – an ECU, controller, flight or motor control unit
• Include the task set and source code, MCU or SoC reference manuals and datasheets, RTOS configuration, linker map, measured timing traces, and the deadlines the system had to meet
• Set up the tools the work needs – cross-compiler, QEMU or an instruction set simulator, trace tools, Python, PDF tools, and a schedulability analysis tool if you use one
• Write five or more tasks, each built on a timing or memory decision or failure on that system (e.g. WCET bounds for park assist routines, core and priority layout for an ADAS controller under memory interference, rare controller resets after a software release)
• Frame each task so the model must produce answer.json with a WCET bound per routine, a core and priority assignment, or a memory layout
• Hide the deciding load where an engineer would have to dig for it – ISR and DMA bursts in the traces, bus or cache interference between cores, a clock setting in the reference manual
• Write a hidden marking script that checks bounds against measured traces within a set tolerance and runs response-time analysis against every deadline and memory limit, scoring 0.0 to 1.0
• Supply your own answer (scoring 1.0) and a naive answer a competent engineer might give first (scoring below 0.3)
• Pitch task difficulty so frontier models solve it in 1 to 4 out of 10 runs, or fail all 10 for the evaluation set
• Hands‑on experience on a real-time embedded system – ECU, controller, flight or motor control unit
• Strong grasp of WCET analysis, response‑time analysis and schedulability
• Experience with RTOS configuration, task priorities and multicore core assignment
• Able to work from MCU or SoC reference manuals, datasheets and linker maps
• Experience analysing timing traces, including ISR and DMA load and bus or cache interference between cores
• Comfortable with cross-compilers, QEMU or instruction set simulators, and trace tools
• Python skills to write automated marking scripts

We can only accept candidates that are willing to work as individual contractors / freelancers.