Performance Software Engineer - Bare-Metal Kernels

Arago; Paris; Sur place; EUR 80 000 - 110 000; Plein temps

Avantages offerts par ce poste

Stock options

Relocation bonus

Moving expense coverage

Healthcare coverage

Pension contributions

Professional development support

25 days PTO

Public transport subsidy

Résumé du poste

Arago, an AI and hardware company, is seeking a Performance Software Engineer to build the core computation software running on Arago's custom AI accelerators. Your work will bridge host systems and the FPGA/silicon, from on-board kernels to tooling for real-time debugging and long-term kernel development.

You will write in C/C++ and assembly, target RISC-V and ARM, optimize for latency and throughput, and collaborate with hardware architects to define interfaces, memory maps, and boot flows.

Qualifications

• Bachelor’s/Master’s/PhD in Computer Science, Computer Engineering, or related field.
• Strong experience in low-level systems programming using C/C++ and assembly, with understanding of how compiled software maps to machine instructions and hardware behavior.
• Bare-metal development experience including startup code, linker scripts, memory layout, MMIO, interrupts/exceptions, timers, synchronization, and peripheral access.
• Strong understanding of computer architecture, including pipelines, caches, memory hierarchies, virtual/physical addressing, atomics, DMA, and performance implications of different access patterns.
• Hands-on experience with RISC-V and/or ARM architectures, instruction sets, calling conventions, ABI concepts, and architecture-specific intrinsics.
• Experience debugging hardware/software interactions using tools such as GDB, JTAG, trace/debug interfaces, simulators, emulators, or FPGA platforms.
• Ability to read hardware specifications, register descriptions, and RTL-level documentation and translate them into robust software implementations.
• Strong performance-analysis and optimization skills, including profiling, disassembly inspection, compiler optimization behavior, and hand-tuned assembly where appropriate.
• Language: English at a proficient level. French is a plus.

Responsabilités

• Develop and optimize low-level software primitives in C/C++, assembly, and architecture-specific intrinsics, primarily for RISC-V and ARM platforms.
• Implement performance-critical kernels, runtime components, hardware abstraction layers, drivers, and firmware operating in bare-metal or highly constrained environments.
• Work closely with hardware architects and RTL/design teams to define and validate hardware-software interfaces, memory maps, register interfaces, interrupts, synchronization mechanisms, and boot flows.
• Analyze and optimize software for latency, throughput, memory footprint, instruction count, and efficient use of processor and accelerator features.
• Bring up and debug software on simulation, emulation, FPGA, and silicon platforms, including low-level hardware/software integration issues.
• Develop validation tests, benchmarks, and diagnostic tools for new processor, DSP, accelerator, and SoC functionality.
• Contribute to architecture decisions around ISA extensions, compiler intrinsics, memory hierarchy, DMA, cache/coherency behavior, and software-visible hardware features.

Connaissances

C/C++

Assembly

Bare-metal development

Computer architecture

RISC‑V/ARM

Debugging hardware/software tools

Performance optimization

English proficiency

Formation

Bachelor’s/Master’s/PhD in Computer Science or Computer Engineering

Outils

GDB

JTAG

trace interfaces

FPGA

simulators/emulators

Description du poste

Arago, an AI and hardware company, is seeking a Performance Software Engineer to build the core computation software running on Arago's custom AI accelerators. Your work will bridge host systems and the FPGA/silicon, from on-board kernels to tooling for real-time debugging and long-term kernel development.

You will write in C/C++ and assembly, target RISC-V and ARM, optimize for latency and throughput, and collaborate with hardware architects to define interfaces, memory maps, and boot flows.