Embedded ML Engineer — Hardware-Aware Model Optimization (Hybrid, Paris)

Zendar; Paris; Hybride; EUR 75 000 - 90 000; Plein temps

Avantages offerts par ce poste

Hybrid work model

Modern office in Paris

Commuter benefits

Meal vouchers

Wellness Pass

Résumé du poste

Zendar seeks experienced ML engineers to optimize and deploy models on heterogeneous embedded platforms, bridging research models and production hardware. You will work at the intersection of ML, compilers, runtimes, and computer architecture to deliver highly optimized implementations.

A core focus is balancing model quality with computational efficiency, collaborating with researchers to develop hardware-aware architectures, identify bottlenecks, and explore architectural changes that improve

Qualifications

• Experience building ML models for embedded platforms.
• Strong PyTorch experience and hands-on model development.
• Familiarity with hardware-aware optimization and neural architecture search.

Responsabilités

• Profile and analyze ML models to identify bottlenecks and data movement.
• Explore trade-offs between model quality and compute cost (latency, throughput, memory).
• Develop hardware-aware optimization and neural architecture search using real hardware measurements.
• Apply quantization, mixed-precision inference, distillation, and model compression techniques.
• Develop and maintain model export, benchmarking, and deployment pipelines across frameworks (PyTorch, ONNX, TensorRT).
• Evaluate deployment strategies for mapping models onto CPUs, GPUs, and AI accelerators.

Connaissances

Python

PyTorch

CUDA

Git

Profiling

Outils

ONNX

TensorRT

CUDA

Description du poste

Zendar seeks experienced ML engineers to optimize and deploy models on heterogeneous embedded platforms, bridging research models and production hardware. You will work at the intersection of ML, compilers, runtimes, and computer architecture to deliver highly optimized implementations.

A core focus is balancing model quality with computational efficiency, collaborating with researchers to develop hardware-aware architectures, identify bottlenecks, and explore architectural changes that improve