Senior Vector Unit Formal Verification Engineer

TechBiz Global GmbH; Helsinki; On-site; EUR 110,000 - 140,000; Full time

Job summary

TechBiz Global is seeking a Senior Formal Verification Engineer to join one of our clients' teams. Reporting to the Vector Unit Verification Lead, you will serve as the formal expert for the VU team, designing scalable testbenches and proving properties for vector pipelines.

You will partner with VU microarchitects to hunt corner-case bugs, write algebraic properties, and drive formal sign-off on high-complexity arithmetic and execution blocks, including RISC-V Vector compliance.

Qualifications

• BS/MS in Computer Engineering, Electrical Engineering or Computer Science, or PhD in related field.
• 5+ years of production-grade hardware verification experience with formal methods.
• Experience applying formal verification to CPU/GPU/DSP pipelines.
• Strong mathematical problem-solving and abstract reasoning abilities.
• Ability to translate counterexamples into actionable bugs for designers.

Responsibilities

• End-to-end formal testbench ownership for vector unit subblocks.
• Datapath and arithmetic verification of IEEE 754 vector units.
• Diagnose and resolve proof convergence failures and state-space issues.
• Develop formal environments to prove RISC-V Vector compliance.
• Mentor team on formal-friendly RTL design and SVA best practices.

Skills

Formal verification

SystemVerilog

SVA (SystemVerilog Assertions)

Python scripting

Debugging

Proof engineering

Education

BS/MS in Computer Engineering, Electrical Engineering, or Computer Science

PhD with research focus on formal methods or computer arithmetic

Tools

Cadence JasperGold/DPV

Synopsys VC Formal

Siemens OneSpin

Job description

TechBiz Global is seeking a Senior Formal Verification Engineer to join one of our clients' teams. Reporting to the Vector Unit Verification Lead, you will serve as the formal expert for the VU team, designing scalable testbenches and proving properties for vector pipelines.

You will partner with VU microarchitects to hunt corner-case bugs, write algebraic properties, and drive formal sign-off on high-complexity arithmetic and execution blocks, including RISC-V Vector compliance.