Senior FPGA Architect & Tech Lead – Multi-Gbps

Luxoft Spain; Lugo; Presencial; EUR 90.000 - 120.000; Jornada completa

Descripción de la vacante

Luxoft Spain is seeking a Principal/Staff FPGA Engineer to own the architecture for high-speed multi-gigabit designs and drive DFX verification. You will shape FPGA strategy, trade IP options, and ensure timing closure for SerDes transceivers, while collaborating with global teams.

You will mentor engineers, lead root-cause debug on silicon and board bring-up, and communicate architecture decisions to stakeholders across the world, using Verilog/SystemVerilog/VHDL-based flows.

Formación

• BS or MS in Electrical and/or Computer Engineering with extensive FPGA experience.
• 5+ years architecting and closing timing on multi-Gbps SerDes FPGA designs.
• Expertise with Verilog/SystemVerilog and/or VHDL for high-speed designs.
• Experience with FPGA transceivers, hard IPs and PLLs, timing closure.
• Experience with Ethernet PHYs and IP stacks at high speeds.
• Experience with optical interfaces (SFPs/QSFPs).
• Experience with AMD/Altera FPGA toolchains and floorplanning.
• Experience with formal verification and/or UVM.
• Strong mentorship and cross-team communication.
• Ability to take FPGA designs from architecture to volume production.

Responsabilidades

• Define and drive end-to-end FPGA architecture for multi-gigabit designs.
• Make/buy tradeoffs on IP, floorplanning and timing closure strategy.
• Lead DFX approach and verification using industry tools.
• Serve as final technical escalation for FPGA design and debug.
• Mentor other FPGA engineers and lead root-cause debug.
• Collaborate with global stakeholders on architecture decisions.

Conocimientos

Verilog/SystemVerilog

VHDL

FPGA timing closure

Multi-Gbps SerDes FPGA design

Optical interfaces (SFP/QSFP)

Ethernet IP protocols

AMD/Altera FPGA toolchains

Formal verification/UVM

Git/version control

Mentoring engineers

Educación

Electrical/Computer Engineering degree

Descripción del empleo

Luxoft Spain is seeking a Principal/Staff FPGA Engineer to own the architecture for high-speed multi-gigabit designs and drive DFX verification. You will shape FPGA strategy, trade IP options, and ensure timing closure for SerDes transceivers, while collaborating with global teams.

You will mentor engineers, lead root-cause debug on silicon and board bring-up, and communicate architecture decisions to stakeholders across the world, using Verilog/SystemVerilog/VHDL-based flows.