FPGA Developer – GNSS SDR for Space Sensors (Flexible Hours)

Terma A/S; Søborg; Hybrid; DKK 700,000 - 1,000,000; Full time

Benefits offered by this job

Flexible working hours

Work from home up to 2 days/week

10% pension

Health care and insurance package

Discounts from partners

On-site massage

Job summary

Terma A/S is seeking an FPGA Developer to work hands-on on GNSS-based SDR solutions. You will develop, implement and verify FPGA functionality in a collaborative, cross-disciplinary team of about 10 colleagues and two student workers, contributing from concept to working solution.

The role emphasizes asynchronous clock-domain crossings, metastability mitigation and efficient use of DSP resources, embedded memory and pipelining. Fluency in English is required; Danish is a plus.

Qualifications

• Electrical Engineering degree with at least 5 years of hands-on FPGA development experience.
• Experience handling asynchronous clock-domain crossings in complex designs.
• Familiarity with metastability mitigation and corresponding analysis methods.
• Practical use of pipelining, DSP resources and embedded memory in FPGA implementations.
• Solid understanding of complex arithmetic, frequency-domain analysis and digital signal processing.

Responsibilities

• Develop and verify FPGA functionality, including testbench development.
• Implement signal-processing algorithms in FPGA.
• Design and manage asynchronous clock-domain crossings.
• Apply metastability mitigation techniques and analysis methods.
• Use pipelining, DSP resources and embedded memory in FPGA implementations.
• Collaborate with the platform architect and embedded software developers on the GNSS-based SDR solution.

Skills

FPGA development

Signal processing

Clock-domain crossings

Metastability mitigation

DSP resources

Education

Electrical Engineering degree

Job description

Terma A/S is seeking an FPGA Developer to work hands-on on GNSS-based SDR solutions. You will develop, implement and verify FPGA functionality in a collaborative, cross-disciplinary team of about 10 colleagues and two student workers, contributing from concept to working solution.

The role emphasizes asynchronous clock-domain crossings, metastability mitigation and efficient use of DSP resources, embedded memory and pipelining. Fluency in English is required; Danish is a plus.