FPGA Design Engineer (m/w/d)

A. KAYSER Automotive Systems GmbH; Einbeck; Vor Ort; EUR 50.000 - 70.000; Vollzeit

Benefits dieser Stelle

30 days holiday

Bikeleasing

Flexible working hours

Training and Continuing Education

Mobile working regulation

Employee Discount

Zusammenfassung

A. KAYSER Automotive Systems GmbH in Einbeck is seeking an experienced engineer to develop high-performance, embedded vision systems. Responsibilities include creating high-speed vision systems and implementing image processing algorithms.

The ideal candidate has extensive experience with FPGAs/SoCs, strong knowledge in video processing algorithms, and proficiency in programming languages such as VHDL and Python. The position offers 30 days holiday, flexible working hours, and opportunities for training.

Qualifikationen

• Multiple years of experience with FPGAs/SoCs.
• Strong knowledge of video/image processing algorithms.
• Very good understanding of design and verification methodologies.

Aufgaben

• Complete high-speed Vision systems.
• Developing RTL code and building image processing chains.
• Verifying designs using latest simulation techniques.

Kenntnisse

FPGAs/SoCs

Video/image processing algorithms

High-speed interfaces (MIPI, SDI, Coaxpress)

VHDL

Python

Linux

Tools

Vivado/Libero

ModelSim

GHDL

NCSim

Jira/Confluence

Jobbeschreibung

• Göttingen
• Full-time
• Permanent

At AES Technology GmbH, our passion for cameras drives us to create the vision solutions of the future. By combining cutting-edge image processing techniques with intuitive design, we strive to develop cameras that truly make a difference. As we continue to explore and expand the boundaries of what’s possible in vision technology, we’re looking for people who share our enthusiasm and want to bring fresh ideas to life.

We are the youngest division of AES Technology GmbH, specializing in opto-electronics, and are based in Göttingen. As an innovative and forward‑thinking team, we focus on developing high‑performance, embedded vision systems.

Responsibilities

• Complete High‑speed Vision systems ranging from Cameras and Video Switch Boxes to Displays
• State‑of‑the‑art image processing algorithms - from Idea to Implementation
• HW/SW Co‑design together with Hardware and Software engineers for efficient designs
• Documentation of Requirements, Design development and verification results
• Developing RTL code and building Image processing chains using VHDL
• Verifying the designs using latest simulation techniques such as cocotb
• Integrating the designs on FPGAs/SoCs for optimal timing, performance and resource efficiency optimizations
• Giga‑speed interfaces such as MIPI, SDI, Ethernet and DDR (3/4/LPDDRx) memory controllers

Qualifications

• Solid technical background and expertise built over multi-year experience with FPGAs/SoCs
• Innate passion for technology and keen to work as a team player
• Strong knowledge of video/image processing algorithms
• Working knowledge of high‑speed interfaces (MIPI, SDI, Coaxpress etc.)
• Very good understanding of design and verification methodologies
• Proficiency in programming languages like VHDL, Python and basic knowledge of embedded C
• Expertise to work with Vivado/Libero and their tool sets
• Experience with HDL Simulation tools such as ModelSim, GHDL, NCSim etc.
• Working experience with Linux is nice to have
• Working knowledge of DO‑254 or with Aerospace industry is a nice to have
• Familiarity with Version controlling for software and workspace management tools such as Jira/Confluence
• Very good communication skills as well as English language skills

Benefits

• 30 days holiday
• Bikeleasing
• Flexible working hours
• Training and Continuing Education
• Mobile working regulation
• Employee Discount

Your contact person: Jasper Ludwig

Recruiting & Employer Branding

Phone: [phone]

Note

For reasons of better readability, the simultaneous use of the language forms male, female and diverse (m/f/d) is waived. All references to persons apply equally to all genders. The abbreviated form of language does not imply any valuation, but is merely for editorial reasons.