Design Verification Engineer

Jobtailor; Deutschland; Remote; EUR 60.000 - 78.000; Vollzeit

Zusammenfassung

Jobtailor seeks a talented verification engineer to develop and maintain SystemVerilog/UVM environments for SerDes and PHY blocks. You will write testbenches, coverage models, and assertions, and run simulations to analyze failures and debug RTL/testbench issues.

You will collaborate with design, architecture, and analog teams on block-level and top-level verification, verifying high-speed SerDes IP used in PCIe, Ethernet, and other interfaces with a focus on code quality.

Qualifikationen

• BSc in Electrical Engineering, Computer Engineering or equivalent.
• 0-5 years of experience in digital design or verification (internships, academic projects, or industry).
• Working knowledge of SystemVerilog and basic familiarity with UVM concepts.
• Strong understanding of digital design fundamentals: synchronous logic, FSMs, pipelining, clock domain crossing.
• Good communication skills in English (spoken and written).
• Candidates should preferably be able to reside in Iași.

Aufgaben

• Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks.
• Write testbenches, functional coverage models, and assertions.
• Run simulations, analyze failures, and debug both RTL and testbench issues.
• Collaborate with design, architecture, and analog teams on block-level and top-level verification.
• Verify high-speed SerDes IP used in PCIe, Ethernet, and other industry-standard interfaces.

Kenntnisse

SystemVerilog

UVM

Digital Design Fundamentals

Analytical Thinking

Problem Solving

Communication Skills

Synchronous Logic

Finite State Machines

Clock Domain Crossing

Ausbildung

BSc in Electrical Engineering

BSc in Computer Engineering

Jobbeschreibung

Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks
Write testbenches, functional coverage models, and assertions
Run simulations, analyze failures, and debug both RTL and testbench issues
Collaborate with design, architecture, and analog teams on block-level and top-level verification
Verify high-speed SerDes IP used in PCIe, Ethernet, and other industry-standard interfaces

Requirements

• BSc in Electrical Engineering, Computer Engineering, or equivalent
• 0-5 years of experience in digital design or verification (internships, academic projects, or industry)
• Working knowledge of SystemVerilog and basic familiarity with UVM concepts
• Solid digital design fundamentals: synchronous logic, FSMs, pipelining, clock domain crossing
• Strong analytical and debug mindset - you enjoy getting to the bottom of a problem
• Good communication skills in English (spoken and written)
• Candidates should preferably be able to reside in Iași

Core Competencies

Demonstrates expertise in developing and maintaining SystemVerilog/UVM verification environments, with a strong foundation in digital design principles and the ability to analyze and debug complex issues. Effective collaboration with cross-functional teams and strong communication skills in English are essential.

Highest-signal resume keywords

• SystemVerilog
• UVM
• Digital Design Fundamentals
• Analytical Mindset
• Communication Skills

Hard Skills

• Testbench Development
• Functional Coverage Models
• Assertions
• Simulation Analysis
• Debugging RTL Issues
• Synchronous Logic
• Finite State Machines
• Pipelining
• Clock Domain Crossing

Soft Skills

• Analytical Thinking
• Problem Solving
• Collaboration

Certifications & Qualifications

• BSc in Electrical Engineering
• BSc in Computer Engineering

Industry Keywords

• SerDes
• PHY Blocks
• PCIe
• Ethernet
• Verification Environment