Senior Scientist for Digital Design with focus on RISC-V (all genders)

Senior Scientist for Digital Design with focus on RISC-V (all genders)

Join us to apply for the Senior Scientist for Digital Design with focus on RISC-V (all genders) role at Silicon Austria Labs (SAL).

Are you passionate about shaping the future of embedded computing architectures? Do you have the expertise and ambition to drive innovation in digital IC design? Join us as a Senior Scientist for Digital Design with a Focus on RISC-V and lead the development of cutting-edge, sustainable, and intelligent computing solutions.

We offer a competitive salary starting at a minimum gross of EUR 70,000 annually, based on an All-in contract and bonus, with additional benefits depending on your experience and qualifications.

About Us

Silicon Austria Labs (SAL) is a leading research center for Electronics and Software Based Systems (ESBS) with locations in Graz, Villach, and Linz. SAL conducts research across the entire ESBS value chain, focusing on sensor systems, power electronics, wireless systems, microsystems, and embedded systems, providing innovative solutions for various industries.

Your Future Responsibilities

• Develop sustainable, dependable, and intelligent embedded computing architectures.
• Lead research in VLSI/digital design focusing on RISC-V and related processor architectures and accelerators.
• Create accurate design specifications for digital control blocks.
• Deliver complex digital IPs meeting schedule, area, power, and performance targets.
• Collaborate with verification teams to develop verification plans.
• Work with laboratory teams to create and verify FPGA-based prototypes.
• Partner with industry and academia for collaborative projects.
• Lead research projects and contribute to securing industry funding.
• Publish research findings in journals and conferences.

Your Profile

• PhD in digital IC design with at least 3 years of relevant experience, or MSc with at least 5 years of experience.
• Proficiency in HDLs (SystemVerilog, VHDL).
• Experience in architecture exploration and micro-architecture development.
• Knowledge of on-chip infrastructure (AMBA/PCIe/USB/JTAG, NoC).
• Background in silicon development and digital IP design/integration.
• Experience with back-end tools (synthesis, P&R).
• Skills in Static Timing Analysis and Clock Domain Crossing.
• Expertise in verification (functional and formal).
• Proficiency in scripting languages (Tcl, Python, Perl, MATLAB, Shell).
• Experience with EDA tools from major vendors (Synopsys, Cadence, Mentor).
• FPGA experience (e.g., Xilinx).
• Good command of English; German is a plus.
• Software development skills (bare metal, RISC-V/ARM) are beneficial.
• Proven project management experience.
• Self-organized and capable of working in a dynamic, multicultural environment.

What We Offer

• Full-time, permanent position in Graz.
• Opportunities for career development, training, and international collaboration.
• Flexible work arrangements, including home office options.
• Family-friendly policies and health promotion initiatives.
• Relocation support for non-EU applicants.

Important Notes

A valid work permit for Austria is required for non-EU citizens. Applications without this or sufficient German language skills may not be considered.

Start date: as soon as possible.