Ultra-Low Latency Market-Making Engineer

G-20 Group; Zürich; On-site; CHF 150,000 - 230,000; Full time

Job summary

G-20 Group is hiring a Low Latency Market Making Engineer to design, build, and optimize systems for ultra-fast quote generation and order execution. The role blends software engineering, hardware interaction, and market microstructure, collaborating closely with traders and researchers to achieve best queue positions across venues.

The candidate will optimize the end-to-end path from network input to application, work with FIX/ITCH/Ouch protocols, and explore FPGA integration to minimize

Qualifications

• Strong foundation in computer science or engineering with hands-on software development experience.

Responsibilities

• Design, build, and maintain ultra-low-latency market making systems.
• Profile and optimize tick-to-trade path with focus on CPU cache and memory layout.
• Collaborate with hardware engineers and possibly develop FPGA logic.
• Own exchange connectivity and protocol implementations (FIX, ITCH/OUCH).
• Partner with traders and researchers to implement quoting logic and risk controls.
• Build simulation, backtesting, and replay infrastructure for validation.
• Monitor live systems, diagnose latency issues, and drive root-cause analysis.
• Contribute to capacity planning and hardware upgrade decisions.
• Uphold engineering standards, testing, and safe deployments.

Skills

C++

Linux internals

Low-latency networking

FPGA development

Performance profiling

Communication skills

Education

Degree in Computer Science or related field

Tools

Solarflare/OpenOnload

DPDK

FIX protocol

ITCH/OUCH protocols

Verilog/VHDL

Job description

G-20 Group is hiring a Low Latency Market Making Engineer to design, build, and optimize systems for ultra-fast quote generation and order execution. The role blends software engineering, hardware interaction, and market microstructure, collaborating closely with traders and researchers to achieve best queue positions across venues.

The candidate will optimize the end-to-end path from network input to application, work with FIX/ITCH/Ouch protocols, and explore FPGA integration to minimize