FPGA Design Engineer (VHDL/Verilog) - High-Speed Protocols

Ellisys; Genf; Hybrid; CHF 110,000 - 150,000; Full time

Job summary

Ellisys in Geneva, Switzerland, seeks a highly analytical engineer with a strong programming background in VHDL or Verilog to join our protocol analysis team. You will design software components for protocol analyzers and testers, and handle large data sets with efficient processing.

Candidates should have high-speed logic design experience, familiarity with Xilinx toolchains, and knowledge of USB, Bluetooth or Wi‑Fi protocols.

Qualifications

• Strong programming background in VHDL/Verilog.
• Experience in high-speed logic design.
• Fluent English or French.

Responsibilities

• Designing new software components for our protocol analyzers, traffic exercisers and compliance testers.
• Defining and implementing creative algorithms and infrastructures for capturing, processing, storing and displaying large amount of data.
• Finding clever ways to present complex information.
• Designing robust expert systems to validate complex scenarios.

Skills

VHDL/Verilog

High-speed logic design

Xilinx tools

Gigabit transceivers

Xilinx Zynq SOC

Object oriented design

USB/Bluetooth/Wi-Fi protocols

Analytical

Communication

Team player

English or French

Tools

Xilinx tools suite

Job description

Ellisys in Geneva, Switzerland, seeks a highly analytical engineer with a strong programming background in VHDL or Verilog to join our protocol analysis team. You will design software components for protocol analyzers and testers, and handle large data sets with efficient processing.

Candidates should have high-speed logic design experience, familiarity with Xilinx toolchains, and knowledge of USB, Bluetooth or Wi‑Fi protocols.