Characterization Lead

Kandou AI; Lausanne; Vor Ort; CHF 100.000 - 160.000; Vollzeit

Zusammenfassung

Kandou AI in Lausanne, Switzerland seeks an experienced SerDes and silicon characterization engineer to lead high-frequency channel measurements and data-driven limit setting. You will plan, execute and hand off results for validation and manufacturing, shaping datasheet specifications for next-generation chip-to-chip links.

The role emphasizes deep VNA and S-parameter analysis, jitter and BER assessment, and cross-functional collaboration in a high-tech scale-up environment.

Qualifikationen

• B.S. in Electrical Engineering or equivalent; technical communication skills essential.
• Lead silicon/ SerDes characterization across process, voltage and temperature.
• Establish datasheet limits and guard-bands from measured data.
• Experience with VNA to 50 GHz, de-embedding and mixed-mode S-parameters.
• Ability to derive characterization limits for shipping products.
• Publish patents or papers in channel modeling or SerDes.

Aufgaben

• Lead silicon and channel characterization from plan to hand-off to validation.
• Characterize TX/RX SerDes performance across PVT; derive limits.
• Own measurements to 50 GHz; de-embed and analyze S-parameters.
• Coordinate lab equipment and drive validation milestones.
• Translate measurements into datasheet limits for qualification.

Kenntnisse

SerDes characterization

VNA measurements

Signal integrity

S-parameters analysis

Jitter analysis

BER bathtubs

TX/RX SerDes characterization

PVT shmoos

Ausbildung

BS in Electrical Engineering or equivalent

Tools

VNAs

50 GHz oscilloscope

BERTs

ATE characterization boards

Jobbeschreibung

https://www.thecube.net/events/nyse/ai-factory-data-center-of-the-future/content/Videos/d1ad8af3-1424-4336-a9b3-1d02b5a354b4

we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption

.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

Join Us at Kandou AI

Lausanne, Switzerland | Up to 30% travel, including Taiwan

Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

Responsibilities

• Lead silicon and channel characterization from measurement planning and bench setup through analysis, limit derivation and documented hand-off to validation.
• Characterize TX/RX SerDes performance across process, voltage and temperature: swing, jitter, sensitivity, equalization, adaptation, CDR lock, BER bathtubs and shmoos.
• Own channel measurements to at least 50 GHz, including de-embedding, insertion/return loss, mixed-mode S-parameters and common-mode and mode-conversion behavior.
• Establish reference-paddle baselines and channel classes by gauge, reach and frequency; correlate HTDR-derived metrics with calibrated VNA measurements.
• Derive datasheet limits and guard-bands from measured distributions, accounting for uncertainty, sample coverage and aging; maintain traceable datasets and limit revisions.
• Assess carrier-loading and forwarded-clock tradeoffs using measured channel data and simulation, and translate the findings into supported configurations and characterization limits.
• Characterize power, energy per bit and thermal behavior across operating modes and corners; investigate equalizer noise amplification and channel/thermal interactions.
• Coordinate shared laboratory equipment and characterization milestones with validation teams; lead technical reviews and deliver limits in time for downstream qualification and screening.
• 10 to 14 years of experience in SerDes/silicon characterization and/or high-speed channel and signal integrity characterization following degree completion.
• Direct ownership of a characterization program whose results became datasheet limits or qualification thresholds for a shipping product.
• Strong VNA measurement experience to 50 GHz or beyond, including de-embedding, mixed-mode S-parameters (Sdd/Scc/Scd/Sdc) and insertion/return-loss mask interpretation.
• Hands-on TX/RX SerDes characterization, jitter decomposition, BER bathtubs, PVT shmoos and equalization/adaptation analysis.
• Demonstrated common-mode and mode-conversion measurement depth, with the ability to distinguish channel behavior from fixture and calibration artifacts.
• Statistical characterization and guard-band derivation across corners, with clear treatment of measurement uncertainty, sample size and aging.
• Experience with VNAs, oscilloscopes of at least 50 GHz bandwidth, BERTs, jitter instrumentation, thermal forcing and ATE characterization load boards.
• BS in Electrical Engineering or equivalent, with the technical communication and coordination skills to hand off defensible limits to validation and manufacturing teams.

Useful Experience

• Characterization leadership for shipping 100G/lane or 200G/lane retimers, PHYs, AECs or AOCs.
• Deep mixed-mode characterization where common-mode behavior affects information transport and link margin.
• Experience producing datasheet limits that a separate validation team independently qualified.
• Multi-carrier or proprietary coding schemes, including OFDM-style subcarriers and space-time coding, and their characterization implications.
• Published work or patents in channel modeling, de-embedding or SerDes characterization.
• MS or PhD with a concentration in communications, RF/microwave engineering or signal integrity.

If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would love to hear from you.