SysVerilog / UVM Design Verification Engineer (Remote)

Entegee; Montreal; Remote; CAD 100,000 - 125,000; Full time

Job summary

A leading company seeks a Design Verification Engineer to work remotely on verification projects. The role requires expertise in SystemVerilog and UVM, with tasks including design verification and developing test benches. Benefits included health insurance, paid leave options, and a 401K plan.

Benefits

Medical insurance

Dental insurance

Vision insurance

Life insurance

Short-term disability

Voluntary benefits

EAP

Commuter benefits

401K plan

Paid leave options

Qualifications

• Proficiency in SystemVerilog.
• Experience with UVM.
• Skilled in developing test benches.

Responsibilities

• Perform design verification using SysVerilog and UVM.
• Collaborate remotely, with potential onsite visits if required.

Skills

SystemVerilog

UVM

Test benches

Job description

Summary : Seeking a Design Verification Engineer with expertise in SysVerilog and UVM for remote work on verification projects.

Requirements :

• Proficiency in SystemVerilog
• Experience with UVM
• Skilled in developing test benches

Responsibilities :

• Perform design verification using SysVerilog and UVM
• Collaborate remotely, with potential onsite visits if required

Pay Details : $54.00 to $72.00 per hour

Benefit offerings include medical, dental, vision, life insurance, short-term disability, voluntary benefits, EAP, commuter benefits, and a 401K plan. Paid leave options such as Sick Leave, holiday pay, and other paid leaves as per law are available.

Equal Opportunity Employer / Veterans / Disabled

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• Los Angeles City Fair Chance Ordinance
• Los Angeles County Fair Chance Ordinance