Staff Verification Engineer, ML IP

Qualcomm; Markham; On-site; CAD 90,000 - 120,000; Full time

Job summary

A leading technology company is seeking an ASIC design verification engineer to join their AI HW team in Canada. This role involves working through design challenges, developing verification strategies, and ensuring high performance in ML hardware solutions. Candidates should have a strong background in digital design, UVM, System Verilog, and relevant experience in ASIC verification.

Qualifications

• 4+ years in ASIC design, verification, validation, integration.
• Strong UVM and System Verilog skills required.
• Comfortable analyzing coverage and debugging.

Responsibilities

• Develop the multimedia and compute subsystem verification strategy.
• Resolve design or verification problems applying ASIC practices.
• Write tests and regressions to identify bugs.

Skills

Digital design concepts

UVM

System Verilog

Bus protocols

Perl

Python

Communication

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

UVM testbenches

Verification environment tools

Job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Are you a creative engineer looking for challenges?

Want to develop technologies that improve people’s everyday life?

Qualcomm AI HW team is looking for a strong ASIC design verification engineer.

Join our effort in developing world class ML HW solutions and push the boundaries on features and performance.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

As a member of the team, your responsibilities include:

• Work closely with design, architects, and verification leads to develop the multimedia and compute subsystem integration verification strategy and test plan
• Create verification environment using UVM/System Verilog
• Resolve architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision
• Write tests and regressions to identify any bugs in own work and helps more junior team members do the same
• Develop C reference model
• Interpret the results of performance checks and identify issues
• Communicate directly with lead on any significant deviations from the Plan of Record for assigned block in a timely manner
• Perform RTL code coverage, assertion coverage, functional coverage, and gate level simulations
• Employ power aware verification technique to verify low power design features
• Identify opportunity for productivity improvements. Drive and adopt new verification methodologies and flows for efficiency improvements

Required Competencies

• Thorough understanding of Digital design concepts
• Strong UVM, System Verilog skills
• Understanding of Bus protocols like AHB/AXI
• Perl, python scripting experience
• Quick understanding of Specs and Standards and developing relevant and thorough test plans
• Experienced in developing monitors, scoreboards, sequencers and sequences and various aspects of the UVM testbenches
• Candidates should be comfortable checking builds, navigating test benches, analyzing coverage, and adding or enabling extra debug
• Strong communication skills and works well in a team environment

Preferred Qualifications

• 5+ years ASIC design, verification, or related work experience.

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