Staff Digital Verification Engineer-Lead Role

Renesas Electronics; Montreal; Remote; CAD 100,000 - 130,000; Full time

Job summary

A leading global semiconductor company is seeking a Staff Digital Verification Engineer to enhance its design and verification team. This role involves developing mixed-signal ASICs, improving the UVM test environment, and mentoring junior engineers. Candidates should have extensive experience in ASIC verification and a strong educational background in engineering.

Qualifications

• 8+ years of practical design verification experience.
• Experience with functional coverage-driven verification sign-off.
• Experience contributing to verification plans.

Responsibilities

• Verification of mixed-signal ASICs in a SV UVM environment.
• Implementing test cases based on functional specifications.
• Leading the verification of small projects.

Skills

SystemVerilog UVM

ASIC verification

Debugging

Functional coverage

Mentoring

Education

Bachelor’s degree in Electrical, Computer, or Software Engineering

Tools

Synopsys

Cadence

Unix/Linux

Python

Job description

Our Ottawa office is looking for a talented Staff Digital Verification Engineer to join our team.

The position is open to remote work in Canada, with strong preference given to candidates in Montreal, Ottawa, and Toronto. After joining our team, you will be developing industry-leading mixed-signal Application Specific Integrated Circuits in a flexible work environment. You will be part of a growing design and verification team, giving you a chance to make a significant impact. As a member of the verification team, you will be responsible for improving and maintaining our UVM test environment, creating new test cases, and debugging mixed-signal chips in digital simulation.

Responsibilities:

1. Verification of mixed-signal ASICs in a SV UVM environment.
2. Implementing test cases based on functional specifications and test plans.
3. RTL and possibly gate-level debugging of mixed-signal ASICs.
4. Implementing functional coverage and assisting designers in reviewing code coverage.
5. Leading the verification of small projects.
6. Mentoring less experienced engineers.

Qualifications:

• Bachelor’s degree or equivalent in Electrical, Computer, or Software Engineering.
• 8+ years of practical design verification experience using SystemVerilog UVM and ASIC verification.
• Experience with functional coverage-driven verification sign-off.
• Experience contributing to verification plans.

Preferred Skills:

• Knowledge of PLLs.
• Experience with Synopsys and/or Cadence simulation tools.
• Ability to work in a Unix/Linux environment.
• Proficiency with scripting languages such as Python.
• Experience with mixed-signal design modeling and debugging.

Company Description:

Renesas is a leading global semiconductor company dedicated to developing a safer, healthier, greener, and smarter world. Our products span automotive, industrial, infrastructure, and IoT markets, including MCUs, SoCs, analog, and power products. With approximately 21,000 employees across more than 30 countries, we embody a culture of transparency, agility, innovation, and entrepreneurship. We are committed to diversity and inclusion and aim to build a sustainable future through technology. Join us to be part of what's next in electronics and the world.