Staff FPGA Engineer

Cognichip; Toronto; On-site; CAD 120,000 - 160,000; Full time

Job summary

Cognichip is looking for a Staff FPGA Design Engineer in Toronto to redefine AI chip design through collaboration and innovation. You will work on modern EDA workflows, embedding chip design expertise in AI systems, and designing complex datasets. The ideal candidate has a Master’s in Computer Science or Electrical Engineering and 10–15 years of experience in RTL design, along with proficiency in tools like Vivado and Quartus. The role offers a hybrid schedule with a collaborative, high-trust culture.

Qualifications

• Master’s degree in a related field is required.
• 10–15 years of experience in RTL design or related.
• Deep expertise with AMD/Xilinx and Altera/Intel ecosystems.

Responsibilities

• Serve as domain expert in AI chip design.
• Architect modern EDA workflows.
• Guide generation of robust UVM testbenches.

Skills

Expertise in RTL design

Proficiency in SystemVerilog

Excellent communication skills

Familiarity with EDA workflows

Education

Master’s in Computer Science or Electrical Engineering

Tools

Vivado

Quartus

Python

TCL

Job description

Staff FPGA Design Engineer

Why This Matters: At Cognichip, we’re not just building AI—we’re redefining what’s possible at the nexus of silicon design and machine learning. In this role you will fuse chip design expertise with cutting‑edge machine learning to create intelligent, end‑to‑end silicon design flows.

Responsibilities

• Serve as the domain expert, embedding chip design intuition into a team creating AI chip design assistants.
• Architect modern EDA workflows, from spec to bitstream.
• Drive the development of agentic AI systems capable of authoring syntactically and semantically correct RTL, manage IP integration, and constructing processor‑based designs.
• Create an ecosystem of libraries, tools, agents, workflows, and benchmarks to increase design velocity.
• Design and synthesize high‑quality, complex datasets (RTL, IP, constraints, failure modes) to train models on hardware physics and logic.
• Define rigorous verification standards and guide the agent in generating robust UVM testbenches, assertions, and coverage models to ensure generated designs are correct‑by‑construction.

Qualifications

• Master’s in Computer Science, Electrical Engineering, or a closely related field.
• 10–15 years of experience in RTL design, or a combination of design and verification.
• Deep expertise with AMD/Xilinx (Vivado, Vitis) and Altera/Intel (Quartus) ecosystems, including SoC and complex IP integrations.
• Knowledge of industry‑standard communication protocols (AXI, Ethernet, PCIe, DDR5, SPI, I2C, NoC, etc).
• Proficiency in SystemVerilog, Python, and TCL.
• Excellent written and verbal communication skills, especially to convey chip design knowledge to software engineers and AI scientists.
• Comfortable working in a dynamic, research‑heavy AI‑oriented startup environment.

Bonus Points

• Personal projects showcasing innovation, creativity, and continuous learning.
• Knowledge of open‑source tools and contribution practices (Verilator, CocoTB, Yosys, OpenSTA, etc).
• Experience with multiple areas of chip flow (RTL design, validation, synthesis, physical design, etc).
• Demonstrated coursework or project experience in machine learning and/or deep learning.

Work Culture

We’re a fast‑moving AI startup with a collaborative, high‑trust culture. You’ll work with top‑tier engineers, scientists, and builders—solving hard problems that sit at the intersection of cloud computing, AI, and chip design. We value technical excellence, ownership, and the freedom to experiment.

Location & Schedule

This position is available in Toronto. We have a hybrid schedule with four days in office and one day remote.