Staff ASIC Digital Design

Synopsys, Inc.; Ontario; Hybrid; CAD 80,000 - 130,000; Full time

Job summary

An established industry player is seeking a highly motivated Staff Digital Design Engineer to join their innovative team. This role focuses on developing and verifying cutting-edge ASIC designs, particularly in high-speed serializer and data recovery circuits. You will collaborate with engineers to enhance existing SERDES PHY IPs and guide junior peers while contributing to the advancement of next-generation products. With a commitment to high-quality designs and a dynamic work environment, this position offers an exciting opportunity to drive technological innovation and make a significant impact in the field of digital design.

Benefits

Health benefits

Wellness programs

Financial benefits

Professional growth opportunities

Qualifications

• 5+ years of digital design and verification experience required.
• Proficiency in Verilog and knowledge of back-end synthesis tools needed.

Responsibilities

• Develop and verify ASIC RTL designs at chip and block levels.
• Collaborate with Application Engineers to resolve technical issues.

Skills

Verilog

Digital Design

Problem-solving

Communication Skills

Teamwork

Education

BSEE

MSEE

Tools

Back-end synthesis tools (DC/PT)

Shell

Perl

Python

TCL

Job description

Position: ASIC Digital Design, Staff

Locations: Mississauga, Markham, Ottawa, Canada Remote

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

We are seeking a highly motivated and innovative Staff digital design engineer with extensive knowledge of ASIC development flow. The ideal candidate is passionate about technology, driven by challenges, and eager to work on cutting-edge SerDes products. You have a solid theoretical and practical background in high-speed serializer and data recovery circuits, and you thrive in a fast-paced, dynamic environment. You bring a wealth of experience in digital design and verification, and you are proficient in Verilog. You are a proactive problem-solver, capable of working independently and as part of a team, with the ability to guide junior peers and network with senior internal and external personnel. Your excellent communication skills enable you to interact effectively with different design groups and customer support teams. You are self-motivated, proactive, and committed to producing high-quality designs while meeting tight deadlines.

What You’ll Be Doing:

• Developing and verifying ASIC RTL designs at both chip and block levels.
• Writing block-level test cases, including constrained directed random tests.
• Implementing digital design methodologies, DFT insertion, and synthesis constraints and flows.
• Enhancing and maintaining existing SERDES PHY IPs for multiple protocols.
• Collaborating with Application Engineers to resolve technical issues and provide customer support.
• Guiding junior peers and networking with senior personnel within and outside the functional area.

The Impact You Will Have:

• Driving the development of high-performance, low-power silicon IP solutions.
• Contributing to the advancement of next-generation NRZ and PAM-based SerDes products.
• Enhancing the capabilities of our SoC solutions to meet unique performance, power, and size requirements.
• Enabling faster time-to-market for differentiated products with reduced risk.
• Improving the functionality and performance of prototype test-chips through rigorous testing.
• Supporting the continuous innovation and technological advancement at Synopsys.

What You’ll Need:

• BSEE or MSEE with a minimum of 5 years of digital design and verification experience.
• Proficiency in Verilog, with good knowledge of back-end synthesis tools (DC/PT).
• Experience in writing block-level test cases and constrained directed random tests.
• Knowledge of digital design methodologies, ATE production testing, DFT insertion, and synthesis constraints and flows.
• Scripting experience in Shell, Perl, Python, and TCL is a plus.

Who You Are:

• Self-motivated and proactive, capable of working independently and as part of a team.
• Excellent communication skills for interacting with different design groups and customer support teams.
• A problem-solver who resolves issues in clever ways and exercises impartial judgment.
• A team player who contributes to the success of the team and guides junior peers.

The Team You’ll Be A Part Of:

You will be part of an experienced mixed-signal design and verification team, targeting the next generation NRZ and PAM-based SerDes products. Our team is composed of veteran digital and mixed-signal engineers who are committed to delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips. We foster a collaborative and dynamic environment that provides continuous training and professional growth opportunities.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please [e-mail].