STA/Constraints Engineer

AMD; Vancouver; Hybrid; CAD 90,000 - 130,000; Full time

Job summary

AMD in Vancouver, BC is seeking an experienced STA/Constraints Engineer to own timing constraints and signoff for SOC and sub-system integration. You will collaborate with Fellows, Principal Engineers, and global teams across Physical Design, Timing Analysis, Synthesis, and PD to mentor design engineers.

The role requires strong scripting in Perl/TCL/Shell/Python, Verilog RTL experience, and a track record in large digital ASIC projects.

Qualifications

• Industry experience in STA, constraints and timing signoff.
• Proficient with PD tools like SNPS PT/GCA and ICC2/FC.
• Strong scripting with Perl/TCL/Shell/Python and Verilog RTL design.
• Excellent presentation and communication skills.
• Experience with Verilog RTL design and large digital ASIC projects.
• Physical design experience is a plus.
• Synthesis or physical implementation experience.
• Lower power design methodology knowledge.
• Strong English speaking and writing skills.

Responsibilities

• Own end-to-end delivery of designs (SOC and sub-system) from timing constraints to timing signoff.
• Collaborate with SOC Architecture for clocks and STA timing targets.
• Prepare and ensure correct SDC setups for clocks.
• Evaluate timing margins (LVF/SSTA/Variations) with timing teams.
• Understand project milestones and deliver FCT closure.
• Collaborate with CAD/EDA vendors to strengthen timing closure methodologies.
• Coordinate with RTL/PD teams for CDC, lint, and netlist quality checks.
• Develop SDC, perform STA analysis, and shift-left timing closure.

Skills

STA experience

Constraints

Timing signoff

SNPS PT/GCA

ICC2/FC

Perl scripting

Python scripting

Verilog RTL

ASIC design

Physical design

Synthesis

Low power design

English communication

Project scheduling

Education

Microelectronics / IC Science (Bachelor/Master)

Tools

SNPS PT/GCA

ICC2/FC

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. Person will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.

KEY RESPONSIBILITIES:

• Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
• Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
• Understanding clock design requirements and making sure they are correctly set up in SDC.
• Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
• Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
• Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
• Responsible for cdc/lint, timing closure, lower power implementation and netlist quality checkwith RTL designer and PD team.
• Work on SDC development, STA (Static Timing) analysis, shift left of timing closure, CDC (Clock Domain Crossing).

PREFERRED EXPERIENCE:

• Industry experience in STA, constraints and timing signoff.
• Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
• Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
• Excellent presentation and inter-communication skills.
• Experience with Verilog RTL design/implementation and has experience of large digital ASICproject.
• Experience with physical design is a plus.
• Has Synthesis or physical implement experience.
• Experience with lower power design methodology.
• Good English skills on talking, presentation and writing documents.
• Good communication and strong sense of responsibility, task scheduling, and timemanagement.

ACADEMIC CREDENTIALS:

• Bachelor/Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.

LOCATION: Vancouver, BC

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.