Sr. Staff Physical Design Methodology Engineer (Toronto)

Lightmatter; Toronto; On-site; CAD 103,000 - 155,000; Full time

Job summary

A leading company in AI data center infrastructure is seeking a Sr. Staff Physical Design Methodology Engineer in Toronto. The role involves developing methodologies for chip design, ensuring power and area estimations, and collaborating with multiple teams. Candidates should have extensive experience in ASIC designs and a strong background in Electrical Engineering. Join a team passionate about innovation and making impactful contributions to the future of computing.

Benefits

Comprehensive Health Care Plan

Retirement Savings Matching Program

Life Insurance

Generous Time Off

Paid Family Leave

Short Term & Long Term Disability

Training & Development

Commuter Benefits

Flexible, hybrid workplace model

Equity grants

Qualifications

• At least 12 years of industry experience as a Physical Design Engineer.
• Multiple complete tapeouts required.

Responsibilities

• Develop flows and methodologies for Static Timing Analysis and Power Analysis.
• Implement the physical design flow from synthesis to tapeout.

Skills

Teamwork

Collaboration

Problem Solving

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

CAD tools

Python

TCL

Job description

Sr. Staff Physical Design Methodology Engineer (Toronto)

Sr. Staff Physical Design Methodology Engineer (Toronto)

1 week ago Be among the first 25 applicants

Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads.

Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter!

If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders.

Lightmatter is (re)inventing the future of computing with light!

Lightmatter builds chips for artificial intelligence computing. Our architecture leverages unique properties of light to enable fast and efficient inference and training engines. If you're a collaborative engineer or scientist who has a passion for innovation, solving challenging technical problems and doing impactful work...work like building the world's first optical computers, consider joining the team at Lightmatter!

Come help us build high performance ASICs for the next generation of AI acceleration systems. In this role, you will be responsible for physical design in leading edge CMOS technology. This includes synthesis through place and route, timing closure, and tapeout signoff.

Responsibilities

• Develop flows and methodologies for one or more of the following:
  
  

Top Level/Full Chip Static Timing Analysis

Power, IR and EM Analysis

Top Level/Full Chip Integration

• Provide power and area estimations for major chip functions
• Perform physical verification to ensure designs are DRC and LVS clean
• Perform power grid verification
• Implement the physical design flow from synthesis to tapeout
• Work with RTL designers to define floorplans, synthesize design, close timing and meet DFT goals
• Work with foundry to define design guidelines
• Scripting and automation of design flow
  
  

Qualifications

• BS or higher degree in Electrical Engineering (or other related fields)
• At least 12 years of industry experience working as a Physical Design Engineer on ASIC designs
• Multiple complete tapeouts
• Fluency in English, both written and verbal
• Experience with industry standard CAD tools and flows
• Experience in Python, TCL or other scripting environments
• Experience in both ASIC and semi-custom COT flow
• Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields
  
  

Preferred Qualifications

• MS in Electrical Engineering (or related fields)
• Experience working on ASIC designs with multiple production-quality ASIC tapeouts
• Experience interfacing with fab and packaging house
• Deep Understanding of all aspects of Physical construction, Integration, Power analysis and Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
• Proven Knowledge of Basic SoC Architecture and HDL languages like System Verilog and chipware components to work hand in hand with RTL designers
• Ability to react to change and thrive in a startup fast-paced environment
  
  

Benefits

• Comprehensive Health Care Plan (Medical, Dental & Vision)
• Retirement Savings Matching Program
• Life Insurance (Basic, Voluntary & AD&D)
• Generous Time Off (Vacation, Sick & Public Holidays)
• Paid Family Leave
• Short Term & Long Term Disability
• Training & Development
• Commuter Benefits
• Flexible, hybrid workplace model
• Equity grants (applicable to full-time employees)
  
  

Benefits eligibility may vary depending on your employment status. Lightmatter recruits, employs, trains, compensates, and promotes regardless of race, religion, color, national origin, sex, disability, age, veteran status, and other protected status as required by applicable law.

Export Control

Candidates should have capacity to comply with the federally mandated requirements of U.S. export control laws.

Seniority level

• Seniority level

  Not Applicable

Employment type

• Employment type

  Full-time

Job function

• Industries

  Construction

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