Senior Technical Staff Engineer - Architect (Memory Interconnect)

Microchip Technology; Toronto; On-site; USD 107,000 - 226,000; Full time

Job summary

A technology firm specializing in interconnect solutions is seeking a Memory Interconnect System Architect to lead IP integrations for FPGA products. Candidates should have a robust background in ASIC and FPGA development, with over 12 years of experience. The role involves cross-functional collaboration and strategic architectural development for high-performance systems. A competitive salary and benefits package is offered.

Benefits

Quarterly bonuses

Health benefits from day one

Retirement plans

Stock options

Qualifications

• 12+ years of industrial experience.
• Proven experience in ASIC and FPGA integration.
• Knowledge of system-level performance modeling is advantageous.

Responsibilities

• Lead cross-functional teams to integrate high-performance IP.
• Develop architecture strategies for interconnects.
• Collaborate with architects and back-end teams.

Skills

ASIC and FPGA IP development

Technical leadership

Scripting skills in Perl, Python, Tcl

System-level performance modeling

Education

MSc or higher in EE, CS, CE, or related fields

Tools

Synopsys ASIC flows

Cadence ASIC flows

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth, enrolling over a thousand people annually. We pride ourselves on our commitment to employee development, values-based decision making, and a strong sense of community, driven by our core values, which have earned us numerous awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we achieved record revenue and growth thanks to a great team dedicated to empowering innovation. People like you.

Visit our page to explore exciting opportunities and learn more about our company!

Job Description :

Microchip Technology's FPGA Business group is seeking a highly skilled and experienced Memory Interconnect System Architect to join our dynamic team. The successful candidate will lead cross-functional teams to deliver high-performance IP integrations into our FPGA products, meeting market and customer requirements across various use cases and application spaces.

This position is within the Silicon Architecture team of Microchip’s FPGA Division. Microchip is a major supplier of low-power and highly-reliable FPGAs used in embedded vision, digital signal processing, machine learning, industrial and medical equipment, and satellites. We are also pioneers in embedding RISC-V processors in FPGAs.

The successful applicant will collaborate with other engineering disciplines to model, develop, verify, and integrate interconnect components such as IO, hard Memory IP blocks, and both hard and soft IP solutions, ensuring they work seamlessly with configuration and security features to deliver high-performance FPGA products.

Key Responsibilities :

• Lead cross-functional teams to deliver high-performance IP integrations into Microchip FPGA products.
• Develop architecture and implementation strategies for analog, ASIC, and FPGA design, focusing on high-performance parallel interconnects supporting protocols such as LPDDR, DDR, LVDS, and MIPI.
• Understand customer use cases and the role of IP within overall system architecture.
• Collaborate with other architects, designers, and back-end implementation teams.
• Manage and lead other engineers within the team.

Requirements / Qualifications :

• MSc or higher in EE, CS, CE, or related fields.
• 12+ years of industrial experience.
• Proven experience in ASIC and FPGA IP development, integration, and deployment, including synthesis, constraint management, place & route, floorplanning, timing closure, CDC/RDC.
• Knowledge of system-level performance modeling in TLM, SystemC, or similar tools is advantageous.
• Experience in technical leadership and people management is a plus.
• Familiarity with Synopsys and Cadence ASIC flows.
• Scripting skills in Perl, Python, Tcl are beneficial.

Travel Time : 0% - 25%

Pay Range :

We offer a competitive total compensation package including base pay, restricted stock units, quarterly bonuses, health benefits from day one, retirement plans, and an industry-leading IESPP program with a 6-month look-back feature. The annual base salary range for this position is $107,000 - $226,000, depending on factors such as location, skills, and experience.

Ontario Accommodation :

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