Senior Staff ASIC Design Engineer

Synopsys Inc; Eastern Ontario; On-site; CAD 100,000 - 130,000; Full time

Job summary

A leading company in semiconductor manufacturing is seeking a Senior Staff ASIC Design Engineer. The role involves working with a skilled team on next-generation SerDes products, focusing on digital design and verification. Candidates should have extensive experience in digital design methodologies and proficiency in Verilog. This position offers opportunities for mentorship and collaboration in a dynamic environment, ideal for those who thrive on technological challenges.

Qualifications

• At least 8 years of digital design and verification experience.
• Proficiency in Verilog and VCS, knowledge of back-end synthesis tools.

Responsibilities

• Collaborate with a team on high-end designs from specification to testing.
• Mentor junior team members and support customer interactions.

Skills

Digital Design

Communication

Problem Solving

Education

BSEE or MSEE

Tools

Verilog

VCS

Shell

Perl

Python

TCL

Job description

Join to apply for the Senior Staff ASIC Design Engineer role at Synopsys Inc

Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would work as part of a highly experienced mixed-signal design and verification team, focusing on current and next-generation NRZ and PAM-based SerDes products.

Strong theoretical and practical background in high-speed serializer and data recovery circuits is a plus. The position offers an excellent opportunity to collaborate with an expert team of digital and mixed-signal engineers, responsible for delivering high-end designs from specification to functional and performance testing on prototype chips.

The PHY IP development environment is dynamic and challenging. The candidate will receive initial training from top experts, along with ongoing on-the-job training. The role requires tackling constant technological changes, ownership, and exploring new areas.

Key Qualifications

• BSEE or MSEE with at least 8 years of digital design and verification experience
• Experience in writing block-level test cases, including constrained directed random tests
• Proficiency in Verilog and VCS; knowledge of back-end synthesis tools DC/PT
• Understanding of digital design methodologies, DFT insertion, synthesis constraints, and flows
• Scripting skills in Shell, Perl, Python, and TCL are advantageous
• Solid understanding of digital signal processing and data recovery circuits
• Strong communication skills for collaboration with various teams and customer support
• Self-motivated, proactive, capable of balancing quality and deadlines
• Ability to resolve issues creatively and exercise independent judgment
• Potential to mentor junior team members and network with senior personnel
• Proven ability to deliver results individually and as part of a team

Preferred Experience

• RTL coding, analog modeling, and complex system-level test-bench development in Verilog
• Synthesis constraints, STA resolution, and gate-level simulation troubleshooting
• Design constraints for clock/reset domain crossings and evaluation with CDC/RDC tools
• Supporting and enhancing SERDES PHY IPs for multiple protocols
• Customer support interactions with Application Engineers and collaboration with P&R teams

Additional Details

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Job functions: Design, Consulting, Engineering
• Industries: Semiconductor Manufacturing, Software Development, Computer Hardware Manufacturing