Senior SoC Design Engineer

FHLB Des Moines; Burnaby; On-site; CAD 86,000 - 186,000; Full time

Job summary

Microchip Technology Inc. in Burnaby, BC, is seeking an experienced RTL Design Engineer to work on complex digital ICs for data center solutions. You will design at block to device level using SystemVerilog/Verilog, define features, and document design details for release.

Collaboration across teams and locations is essential for success. The role requires 3–5 years in RTL design, familiarity with ASIC flows, and a proactive approach to debugging and verification.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or equivalent.
• 3–5 years RTL design experience; SystemVerilog/Verilog required.
• Familiar with ASIC design flows, sim/debug, synthesis, timing and revision control.
• Experience with formal verification is an asset.

Responsibilities

• Design complex digital ICs at block, subsystem or device level.
• Define feature sets and document design in engineering and registers docs.
• Support emulation, ASIC lab validation and debugging.
• Collaborate with multiple locations to resolve issues and decisions.
• Interface with architects to justify design trade-offs and read standards.

Skills

RTL Design

SystemVerilog

Verilog

ASIC design flow

Debugging

Analytical skills

Teamwork

Time management

English communication

Scripting basics

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent

Tools

Synopsys Design Compiler

Cadence Incisive

Waveform viewers

Verification tools

Lab validation tools

Job description

Job Description

Division: Microchip Data Center Solutions Business Unit

Location: Burnaby, BC, Canada

The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry’s cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world’s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry’s technology leadership.

Responsibilities

• Design of complex digital integrated circuits at the block, subsystem or device level (100K to 50M+ gates), which are coded in Verilog
• Define subsystem/block feature sets, describe design and implementation details into engineering documents and registers documents
• Support emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds
• Communicate regularly with the design and verification team in multiple locations to resolve issues, communicate status and solve technical problems
• Communicate with architects to justify design implementation decisions and associated trade-overs
• Read and understand applicable storage and computer interface protocol standards

Requirements / Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent
• 3 to 5 years related experience RTL Design - Experience in RTL Design using System Verilog, Verilog is required.
• Experience and understanding of complex ASIC design flows, including block and chip level simulation and debug, logic synthesis, static timing analysis, layout and revision control
• Experience with Formal Verification will be an asset.
• Working knowledge of design and verification tools such as Synopsys Design Compiler, Cadence Incisive, waveform viewers, and other similar tools.
• Scripting and programming skills using csh, bash, perl, python, tcl, etc will be an asset.
• Protocol knowledge and experience in PCI-Express will be an asset.
• Knowledge of AHB/AXI bus protocols is desired.
• Knowledge in logic synthesis and static timing analysis.
• Worked with physical design teams for layout implementation.
• Familiar with low power methodology and flows.
• Excellent analytical and debugging skills and the ability to proactively solve issues
• Good verbal and written communication skills in English will be an asset
• Excellent teamwork and time management skills, self-direction, the ability to work under pressure and the desire to excel in a competitive environment

Travel Time

0% - 25%

Pay Range

The annual base salary range for this position is $86,000-$186,000. *Range is dependent on numerous factors including job location, skills and experience.

Benefits of working at Microchip

• health benefits that begin day one
• retirement savings plans
• industry leading IESPP program with a 6-month look back feature

Company Overview

Microchip's nationally-recognised Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation.

Other Information

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.