RTL Designer

HRB; Canada; Remote; CAD 90,000 - 130,000; Full time

Job summary

A leading organization in Canada seeks an RTL Designer to develop innovative IP for ASICs and FPGAs. The ideal candidate will possess strong communication skills, a critical thinking mindset, and extensive experience in hardware design, specifically using Verilog/SystemVerilog. This role involves designing hardware architectures, simulating tests, and applying Agile development practices, while being part of a collaborative engineering team.

Qualifications

• 5+ years of experience in hardware systems design and performance improvement.
• Expertise in FPGA/ASIC development environment tools.
• Hands-on experience in PCIe PHY and controller IP integration.

Responsibilities

• Design and oversee the evaluation of hardware architectures.
• Simulate, test, debug, and verify hardware designs.
• Apply Agile methodologies and participate in code reviews.

Skills

Communication

Critical Thinking

Problem Solving

Education

B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science

Tools

Verilog

SystemVerilog

Python

C

C++

Job description

To help grow our organization, we are looking for anRTL Designerto contribute to a team developing IP for both ASICs and FPGAs. The ideal candidate is a strong communicator, creative, a critical thinker, and able to analyze and resolve complex issues.

Responsibilities

• • Design, propose, and oversee the analysis/evaluation of hardware architectures
  • Design and code RTL modules written in Verilog/SystemVerilog
  • Simulate and perform hardware-based testing, debug, and verification
  • Scripting and basic software development in support of hardware design
  • Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment

Requirements

• • B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science
  • 5+ years of experience in hardware systems design, analyzing and improving RTL hardware performance and area as well as lab bring-up
  • FPGA/ASIC development environment tools expertise, including design, implementation and debug
  • Strong knowledge with RTL programming languages Verilog/SystemVerilog (preferred), or VHDL
  • Ability to read and write code in Python (C, C++ are assets)
  • Hands on experience in PCIe PHY and controller IP integration and bring-up

Preferred Skills & Experience

• • Deep experience with ASIC and FPGA programming including timing closure, resource management, and using IP libraries highly preferred
  • Working experience with PCIe, UCIe, and HBM will be an asset
  • Experience with Agile development methodologies
  • Experience in technical leadership of small teams