RTL Design - SLSI

TN United Kingdom; Goldstone; On-site; CAD 80,000 - 120,000; Full time

Job summary

An innovative firm is seeking a talented RTL Micro-architecture Design Engineer to contribute to cutting-edge SoC integration projects. This role involves designing and verifying complex digital systems, ensuring optimal performance and power efficiency. You will collaborate with cross-functional teams to produce high-quality documentation and RTL, while also engaging in power reduction strategies. If you have a passion for VLSI design and want to work on impactful projects within a dynamic environment, this position offers an exciting opportunity to advance your career.

Qualifications

• 5 to 15 years of experience in VLSI RTL IP or Subsystem design.
• Strong understanding of AMBA SoC BUS protocols.
• Knowledge in ASIC design flow and debugging tools.

Responsibilities

• Design and verify micro-architecture for SoC subsystems.
• Collaborate with DV teams to improve verification coverage.
• Define constraints for high-speed path timing closure.

Skills

VLSI RTL IP Design

Digital Design Principles

Debugging Skills

SoC Integration

ASIC Synthesis

Power Reduction

Tools

Spyglass

Synopsys DC

Meridian CDC

Cadence/Synopsys/Mentor Simulators

Job description

Position Summary

Secure an optimal digital IP and circuit by understanding required functions to be developed and designing and verifying them in line with the required goals.

Role and Responsibilities

Job Profile – RTL Micro-architecture Design Engineer (SOC Integration)

• 5 to 15 years of work experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU/GPU Subsystem or other Mobile SoC Subsystem.
• Understanding of digital design principles and AMBA SoC BUS protocols, specifically APB, AXI, and AHB.
• Creating micro-architecture and detailed design documents for SoC Subsystem design, considering performance, power, and area requirements.
• Strong debugging skills and extensive experience with DV tools like Verdi, NCSIM.
• Preferred SOC Integration experience at Top Level, Block Level, or Subsystem level.
• Collaborate with DV team to improve verification coverage and work on GLS closure with DV, PD, and Modeling teams.
• Knowledge in clock domain crossing (CDC), linting, UPF, DFT, and multi-voltage rule check analysis.
• Understanding of ASIC synthesis, static timing report analysis, formal checking, etc.
• Define constraints and work with back-end teams to achieve high-speed path timing closure.
• Work abroad.

Additional Roles

GPU Micro-architecture Design Engineer

• Design and collaborate with other architects to define micro-architecture.
• Deliver high-quality micro-architectural documentation.
• Produce RTL that meets PPA goals on schedule.
• Work with GPU/CPU teams to drive power reduction through estimation, analysis, and optimization.
• Collaborate with system architects to define use cases and optimize power and performance.
• Run performance and power models, analyze data, and evaluate trade-offs.

IP Design Micro-architecture Engineer

• Design and collaborate on micro-architecture within IP level.
• Deliver quality documentation and RTL on schedule.
• Drive power reduction and collaborate on bandwidth and performance targets.
• Knowledge in Image Processing and Display architectures is advantageous for senior candidates.
• Understanding of ASIC design flow.
• Working knowledge of C/C++ and Linux, including scripting, is a plus.

Tools and Languages

Tools: Spyglass, Synopsys DC, Meridian CDC, Cadence/Synopsys/Mentor simulators

Languages: Verilog HDL, SystemVerilog, C/C++

Skills and Qualifications

Please visit Samsung membership to review Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are a European Economic Resident, please click here.

Note: If you are not a passport holder of the country for the vacancy, you might need a work permit. Check our Blog for more info.

Do not provide bank or payment details when applying. Applications should be submitted via the 'Apply now' button.

Created on 28/04/2025 by TN United Kingdom