R&D Sr. Staff Design Engineer – DDR/HBM PHY Architecture

Synopsys, Inc.; Markham; On-site; CAD 90,000 - 140,000; Full time

Job summary

An innovative firm is seeking a Senior Staff Design Engineer with expertise in DDR/HBM PHY architecture. This role involves collaborating with a talented architecture team to design cutting-edge products that meet customer specifications. You will leverage your extensive experience in mixed-signal design and RTL logic to tackle complex challenges in the development of high-speed interfaces. Join a dynamic environment where your contributions will drive the future of technology and enhance the performance of next-generation products. If you are passionate about engineering and eager to make an impact, this opportunity is for you.

Qualifications

• 8+ years of experience in PHY architecture or related fields.
• Proficient in RTL design and mixed-signal principles.

Responsibilities

• Translate customer needs into product design features.
• Generate specifications for interface components and operations.
• Collaborate with multi-site teams on design solutions.

Skills

Mixed-signal design

Off-chip signaling

RTL logic design

Design-for-test

Timing analysis

Power analysis

Behavioral modeling

Troubleshooting mixed-signal interfaces

Communication skills

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree (preferred)

Tools

Simulation software

Documentation tools

Job description

R&D Sr. Staff Design Engineer – DDR/HBM PHY Architecture

We’re looking for a PHY architect to join the DDR/HBM PHY architecture team.

In this position, you will be part of an architecture team that plans and executes the design for the next-generation DDR and HBM PHYs in the Synopsys IP portfolio. The job entails working with senior architects to understand standard specifications, evaluate ideas, draft specifications, and enable a larger team of design engineers bringing new ideas into silicon. You’d leverage your understanding of computer architecture, mixed-signal design, off-chip signaling, RTL development, design-for-test, and logical verification to create leading-edge products. Supporting Synopsys’ customers is also an important part of the role. You will join a collaborative, multi-person engineering team engaged in similar activities on related DDR and HBM PHY development projects.

Job Responsibilities:

• With the guidance of a senior architect, understand marketing, customer desires, and standard specifications, then translate those into product design features and functions for ongoing and future designs to create best-in-class products.
• Generate functional descriptions for the product, creating specifications that describe the interface components, operation, structure, and behavioral parameters.
• Develop models representing the performance features of interface design sub-components.
• Solve design execution problems tied to the product definition.
• Perform feasibility studies through the evaluation of trial designs.
• Document results, conclusions, and technical insights into performance, power, area, and functional parameters.
• Interact and communicate with digital design, verification, analog circuit design, and layout teams.

Key Qualifications and Experience:

• Minimum of 8+ years of related experience or an advanced degree with 6+ years of related experience.
• Understanding of high-speed interface principles, such as mixed-signal design and off-chip signaling.
• Skilled in generating and supporting documentation through written specifications and communicating with design teams and external customers.
• Proficiency in RTL logic design, simulation, test planning, and verification of complex IC components.
• Knowledge of design-for-test, timing analysis, power analysis, behavioral modeling, and synthesis constraints.
• Ability to work across multi-site teams to communicate ideas, understand problems, and find solutions.
• Skilled in troubleshooting and debugging mixed-signal interfaces.
• Knowledge of DDR protocols and JEDEC specifications is a plus.
• Experience with GenAI in the design process is a plus.
• Ability to work autonomously with high-level guidance.