Custom Analog Enablement and Methodology, Staff Engineer - 15233

Synopsys Inc; Mississauga; On-site; CAD 120,000 - 190,000; Full time

Benefits offered by this job

Comprehensive health benefits

Financial benefits

Job summary

A global semiconductor leader seeks a seasoned engineering leader to advance analog and mixed-signal IP development. You will define methodologies, enhance workflow, and provide technical leadership to ensure high-quality design outcomes. With over 5 years of experience required, candidates should have expertise in analog/mixed-signal layout and familiarity with industry tools like Synopsys Custom Compiler and Cadence Virtuoso. You'll mentor junior engineers while collaborating with interdisciplinary teams to drive innovative solutions in a fast-paced environment.

Qualifications

• 5+ years in analog/mixed-signal layout or ASIC physical design.
• Deep knowledge of CMOS layout and chip-level integration.
• Proven ability to gather customer requirements and convert them into specifications.
• Ability to gather customer requirements and convert them into technical specs.
• Experience building workflows that improve IP quality, efficiency, and consistency.
• Strong organizational skills and ability to manage multiple initiatives.
• Excellent communication, leadership, and mentoring abilities.

Responsibilities

• Define and deploy advanced layout methodologies.
• Gather requirements, ensuring they drive methodology and workflow development.
• Provide technical leadership, aligning planning to meet project goals.
• Collaborate with Circuit Design, Physical Design, CAD, Product Engineering, and Quality teams.
• Provide technical leadership across distributed teams and track project goals.
• Define, monitor, and analyze performance metrics to drive improvements.
• Create and maintain comprehensive documentation for scalability and reuse.
• Engage with internal partners and external customers as a technical representative.
• Lead innovation in analog/mixed-signal layout flows and automation.
• Mentor and support junior engineers across the organization.

Skills

Analog and mixed-signal layout expertise

Collaboration with interdisciplinary teams

Technical leadership

Mentoring junior engineers

Strong organizational skills

Tools

Synopsys Custom Compiler

Cadence Virtuoso

ICV

Calibre

Job description

We Are

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are

You are a seasoned engineering leader with a passion for advancing semiconductor technology. Your expertise in analog and mixed-signal layout—especially in advanced CMOS, FinFET, and GAA nodes—sets you apart. You thrive in environments where innovation, collaboration, and precision are valued, and you are driven by the challenge of defining scalable methodologies that empower global engineering teams. Your strategic mindset enables you to translate complex technical challenges into actionable workflows, ensuring the highest standards of quality and efficiency. You are skilled at bridging communication between interdisciplinary teams and stakeholders, delivering clarity and aligning objectives. Mentoring is part of your DNA; you take pride in fostering growth in junior engineers and sharing knowledge across the organization. You are comfortable managing multiple priorities, adapting to fast-paced changes, and driving collective excellence. Your technical insight is matched by your organizational skills and your ability to inspire teams to embrace new methodologies and innovative solutions. If you’re committed to pushing the boundaries of analog/mixed‑signal IP development and are ready to make a meaningful impact at a global leader in semiconductor technology, Synopsys is your next destination.

What You’ll Be Doing

• Defining and deploying advanced layout methodologies that accelerate execution, enhance quality, and promote standardized best practices across global teams.
• Gathering customer requirements, translating them into clear technical specifications, and ensuring these specifications drive methodology and workflow development.
• Developing end‑to‑end workflows that enhance quality, consistency, and efficiency across Synopsys IP development.
• Collaborating closely with cross‑functional teams—including Circuit Design, Physical Design, CAD, Product Engineering, and Quality—to enable adoption of methodologies for advanced technology nodes.
• Providing technical leadership across distributed teams, aligning planning and execution to meet project goals.
• Defining, tracking, and analyzing performance metrics to drive continuous improvement and influence future methodology strategy.
• Creating and maintaining comprehensive documentation to ensure clarity, scalability, and long‑term usability.
• Engaging with internal partners and external customers as a trusted technical representative of the Methodology Team.
• Leading innovation in analog/mixed‑signal layout flows, combining industry‑standard tools and internal automation to validate and evolve methodologies.
• Mentoring and supporting junior engineers, enabling skill growth and knowledge sharing across the organization.

The Impact You Will Have

• Accelerating and improving the reliability of analog/mixed‑signal IP development at advanced nodes.
• Driving alignment and quality across global design teams through standardized workflows and strong technical leadership.
• Strengthening collaboration and knowledge transfer across engineering disciplines.
• Influencing organizational and product strategy through methodology innovation and customer insights.
• Increasing transparency and maintainability of workflows through high‑quality documentation.
• Contributing to reinforcing Synopsys’ position as a leader in semiconductor design technology.

What You’ll Need

• 5+ years in analog/mixed‑signal layout or ASIC physical design, with experience in FinFET and advanced nodes strongly preferred.
• Deep knowledge of analog and mixed‑signal CMOS layout, device‑level considerations, and chip‑level integration.
• Strong expertise with industry tools such as Synopsys Custom Compiler, Cadence Virtuoso, ICV, Calibre, and related verification flows.
• Proven ability to gather customer requirements and convert them into technical specifications.
• Demonstrated experience building workflows that improve IP quality, efficiency, and consistency.
• Strong organizational skills, attention to detail, and ability to manage multiple complex initiatives simultaneously.
• Excellent communication, leadership, and mentoring abilities.

Who You Are

• Innovative and proactive in solving complex engineering challenges.
• Collaborative, with a talent for working across interdisciplinary teams.
• Strategic thinker who balances technical depth with big‑picture vision.
• Effective communicator, able to convey technical concepts to diverse audiences.
• Mentor and coach, dedicated to supporting the growth of others.
• Adaptable and resilient in fast‑paced and evolving environments.

The Team You’ll Be A Part Of

You will join the Mixed Signal IP Technology and Methodology Team—an advanced physical design group focused on developing full‑custom analog and ASIC layout solutions for high‑speed integrated circuits. The team is known for its collaborative culture, cutting‑edge tool ecosystem, and strong commitment to innovation. As a Staff Engineer, you’ll work closely with experienced layout engineers, CAD specialists, and circuit designers to help define best‑in‑class methodologies and deliver high‑quality solutions for Synopsys’ global customers.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.