Principal/Team Lead, Digital Verification Engineer (FEC)

ciena; Ottawa; On-site; CAD 133,000 - 213,000; Full time

Benefits offered by this job

Medical Insurance

Dental & Vision

401(K) USA & DCPP Canada

Employee Stock Purchase Plan

Paid Holidays & Leave

Job summary

Ciena is seeking a seasoned Digital Verification Engineer (FEC) in Ottawa to advance verification strategies for Forward Error Correction IP. You will collaborate with design, DSP, and systems teams to verify complex blocks using SystemVerilog, UVM and C++, ensuring thorough coverage.

The role demands 10+ years of verification experience and a strong background in C/C++, SystemVerilog, UVM, and SVA, with leadership to mentor junior engineers.

Qualifications

• 10+ years of verification experience.
• Bachelor's degree in Electrical, Computer or Software Engineering.
• Strong proficiency in C/C++, SystemVerilog, UVM, SVA and simulators.
• Ability to define digital verification and coverage strategies.

Responsibilities

• Read FEC architecture and requirements, collaborate with FEC designers and systems engineers.
• Develop verification, functional coverage and formal verification test plans.
• Validate FEC functional blocks using simulation, formal and coverage methods.
• Create testbench environments, agents, scoreboard and test scenarios with SystemVerilog UVM and C++.
• Perform coverage-driven verification, monitor regressions and debug with designers.
• Provide status updates and communicate risks as needed.
• Mentor and supervise junior verification engineers.
• Communicate clearly with stakeholders to influence decisions.

Skills

C/C++

SystemVerilog

UVM

SVA

Digital verification

Education

Bachelor's degree in Electrical, Computer or Software Engineering

Tools

Jira

Git

Python

Make

Bash

Job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We're a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being-on and off the job. Connect with a career that matters.

How You Will Contribute

At Ciena, we are at the forefront of the telecommunications industry, and our Wavelogic modem family of products plays a crucial role in our success. As a Digital Verification Engineer (FEC), you will be an integral part of a team responsible for implementing innovative verification strategies in order to thoroughly simulate and validate functional blocks and subsystems for Ciena's Forward Error Correction (FEC) IP. Reporting to the ASIC Senior Manager, you will collaborate with a team of Digital Design Engineers, Verification Engineers, and Architects to simulate and validate functional blocks and subsystems.

Responsibilities

• Read and understand the FEC architecture and functional requirements specification document(s) and communicate and collaborate with FEC designers, DSP modelers, FEC verifiers, systems engineers and architects.
• You will be responsible for developing verification, functional coverage and formal verification test plans.
• Thoroughly validate one or more architectural FEC functional blocks using a combination of simulation, formal, and coverage methods.
• Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and C++.
• Perform coverage-driven verification, monitor regressions, and debug failures with the support of the function's designer.
• Provide status updates on verification progress on a regular basis and communicate risks as needed.
• Mentor and supervise junior verification engineers requiring robust understanding of team outputs to foster peers' technical and professional growth.
• Excellent communication and interpersonal skills with demonstrated ability to convey complex technical concepts clearly and effectively influence stakeholders.

The Must Haves

• 10+ years of experience in verification.
• Minimum Bachelor's degree in Electrical, Computer or Software Engineering.
• Significant experience in using C/C++, System Verilog, UVM, SVA, and simulators from major vendors.
• Proven ability to determine comprehensive digital verification and coverage strategies.
• Proven ability to foster a culture of innovation and continuous improvement within the team via demonstrated leadership and communication capabilities.
• Strong decision-making skills with the ability to analyze complex situations, evaluate options and implement effective solutions to meet deliverables.

Assets

• Experience with formal verification methods.
• Strong background in Forward Error Correction (FEC) and/or DSP.
• Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++.
• Proficiency in bug tracking using Jira and source code management and revision tracking using GIT.
• Previous experience leading a team.
• Previous experience mentoring.

Pay Range

Pay Range: The annual salary range for this position in Ottawa is $133,100 - $212,500.

Compensation and Benefits

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

Equal Opportunity and Diversity

Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any acco