Principal Engineer -Design

Microchip Technology Inc.; Saskatchewan; On-site; CAD 120,000 - 180,000; Full time

Job summary

Microchip Technology Inc. in Canada is seeking a Principal Engineer to lead the digital design, DFT, physical implementation, and STA signoff for complex ICs within the CBU Product Development team.

You will drive RTL-to-pre-layout netlist generation, coordinate with RTL/DFT engineers, and ensure on-time delivery across multiple macros and subsystems using Cadence and Synopsys tools. Excellent analytical and scripting skills are required.

Qualifications

• Bachelor’s or Graduate Degree in Computer Sciences, Electrical/Electronics/VLSI Engineering.
• 10 years of experience in synthesis, STA and Formal Verification with mainstream tools.
• Excellent analytical and debugging skills.
• Strong coding and scripting (TCL, Perl or Python).
• Proven ability to thrive on, learn and adapt to new methodologies and technologies.
• Hands on experience in RTL Design, synthesis, low-power logic insertion using UPF/CPF and STA signoff of Macro’s and SoC Level.
• Good understanding of timing models, DFT, libs, hierarchical budgeting flows.
• Tapeout experience of 1 or more projects with 16nm or smaller silicon process technologies.
• Hands-on experience with synthesis tools like Cadence Genus OR Synopsys-DC/FC.
• Good verbal and written communication skills in English, strong interpersonal skills.

Responsibilities

• Develop macro constraints (Synthesis, STA & Layout) for high-speed macros and subsystems.
• Achieve STA sign-off for all design levels across multiple modes and corners.
• Develop/understand RTL Synthesis flows and improvements.
• Learn new flows quickly and influence quality of results.
• Collaborate with RTL and DFT engineers and project teams to ensure proper constraints and deliverables.
• Ensure deliverables quality pre/post netlists (CLP, LEC, tool checks).
• Coordinate with APR team for floorplanning and macro placements quality.

Skills

RTL Design

Synthesis

STA

DFT

Timing models

Python

TCL scripting

Cadence Genus

Synopsys-DC/FC

Education

Bachelor’s or Graduate Degree in Computer Sciences, Electrical/Electronics/VLSI Engineering

Tools

Cadence Genus

Synopsys-DC/FC

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Job Description

Microchip’s Communications Business Unit (CBU) is a premier supplier of 100Gbps+ Optical Networking and Connectivity Solutions for Telecom and Hyperscale Data Center Networks. Our state-of-the-art devices power high-bandwidth, cloud-based applications including streaming services, social media platforms, and video conferencing worldwide.

The CBU Product Development team drives the full semiconductor R&D lifecycle—from initial concept, design, and implementation to embedded software integration, system validation lab testing, and mass-market production release. Working with the latest tools and methodologies in advanced process nodes, our experienced team delivers industry-leading network devices.

We are seeking a Principal Engineer to join the CBU Product Development team. In this role, you will lead the digital design, DFT, physical implementation, and static timing analysis (STA) of integrated circuits at both the block and top chip levels.

Working alongside our implementation team on advanced technology nodes, you will drive RTL-to-pre-layout netlist generation and own STA signoff across multiple macros, subsystems, and full-chip designs using industry-standard Cadence and Synopsys synthesis suites.

Responsibilities

• Responsible to develop macro constraints (Synthesis, STA & Layout), ram generations, flow configuration for High-speed complex macros and Subsystems.
• Responsible for STA sign off for all levels of design hierarchy for multiple modes and multiple corners (MMMC)
• Responsible to develop/understand flow and methodology for doing RTL Synthesis.
• Ability to pick up new flows, learn on the job and influence QOR is a must.
• Co-work with RTL and DFT engineers and interact with project teams to ensure the right constraints/deliverables are in place.
• Ensure the Quality of deliverables pre/post netlists (CLP, LEC, In-house tool checks)
• Close interactions with APR team to ensure that floorplanning/macro placements/quality of deliverables are in the right direction.

Requirements/Qualifications

Qualification:

• Bachelor’s or Graduate Degree in: Computer Sciences, Electrical/Electronics/VLSI Engineering
• 10 years of experience in synthesis, STA and Formal Verification with mainstream tools.
• Excellent analytical and debugging skills and the ability to proactively solve issues
• Strong coding skills and scripting skills (TCL, Perl or Python).
• Proven ability to thrive on, learn and adapt to new methodologies and technologies
• Hands on experience in RTL Design, synthesis, low-power logic insertion using UPF/CPF and STA signoff of Macro’s and SoC Level.
• Good understanding of timing models, DFT, libs, hierarchical budgeting flows.
• Hands-on to deliver solutions to critical design and execution issues related to synthesis.
• Tapeout experience of 1 or more projects with 16nm or smaller silicon process technologies
• Hands-on experience with synthesis tools like Cadence Genus OR Synopsys-DC/FC.
• Good verbal and written communication skills in English, strong interpersonal skills

Travel Time

0% - 25%