Memory Layout Engineer

Value Innovation Labs; Ottawa; On-site; CAD 90,000 - 130,000; Full time

Job summary

Value Innovation Labs is seeking a Memory Layout Engineer to drive layout development and physical verification for next-gen memory blocks in an SoC context.

The role requires hands-on experience with memory architecture, signoff closure, and cross-functional collaboration with circuit and process teams. Strong debug skills and familiarity with TSMC 7nm FinFET and 6nm–3nm nodes are essential.

Qualifications

• Experience in memory layout development for advanced-node processes.
• Proven ability in physical verification and top-level integration for SoC blocks.
• Solid debugging and problem-solving skills with cross-team collaboration.

Responsibilities

• Layout optimization for Sense Amplifiers, Control Circuits, I/O Blocks, Bit-Cell Arrays & Decoders.
• Top-level memory integration within SoC environments.
• Physical verification and signoff closure; DRC, LVS, density checks.
• IR drop and EM analysis and mitigation; ensure reliability.
• Collaborate with Circuit Design, Physical Design & Process teams.
• Hands-on experience with TSMC 7nm FinFET; knowledge of 6nm–3nm nodes.

Skills

Memory layout

Physical verification

Top-level memory integration

DRC LVS density checks

EM analysis

TSMC FinFET experience

Debugging

SoC integration

Education

Bachelor’s/Master’s in Electrical/Electronics Engineering

Job description

We are looking for a highly skilled Memory Layout Engineer with strong expertise in advanced-node technologies and hands-on experience in memory layout development, physical verification, and top-level integration.

• Layout optimization for Sense Amplifiers, Control Circuits, I/O Blocks, Bit-Cell Arrays & Decoders
• Top-level memory integration within SoC environments
• Physical verification and signoff closure
• DRC, LVS & Density Checks
• IR Drop and Electromigration (EM) analysis and mitigation
• Collaborate with Circuit Design, Physical Design & Process teams
• Hands-on experience with TSMC 7nm FinFET
• Physical Verification – DRC, LVS, Density
• Strong debugging and problem-solving skills
• Experience with TSMC 6nm / 5nm / 4nm / 3nm
• Strong understanding of memory architecture and layout methodologies
• Education: Bachelor’s/Master’s in Electrical/Electronics Engineering or related field.
• Onsite Requirement: Candidates must be able to commute to the Ottawa, Ontario location.