Lead Digital Verification Engineer

Cadence; Mount Royal; On-site; CAD 89,600 - 166,400; Full time

Benefits offered by this job

RRSP

TFSA

Employee Stock Purchase Plan

Health coverage

Life insurance

Disability insurance

Travel medical coverage

Job summary

Cadence is seeking a Lead Verification Engineer in Montreal, Canada to join our growing team responsible for verifying digital RTL and developing reusable verification components and environments. You will contribute to test plans, functional and code coverage, and drive verification flows to meet project timelines.

You will work with design and verification teams across the globe, communicating progress clearly and supporting Cadence standards, with up to 5% travel as needed.

Qualifications

• Bachelor degree in Electrical/Computer Engineering or Computer Science.
• Understanding of verification architecture and methodologies.
• Understanding of Metric Driven Verification.
• Understanding of Universal Verification Methodologies (UVM).
• Knowledge of functional coverage and checks planning.
• Knowledge of SystemVerilog Assertions (SVAs).
• Understanding of digital design flow.

Responsibilities

• Verify digital RTL and develop reusable verification components and environments.
• Contribute to verification flow development, test plan development and execution, coverage closure.
• Communicate project progress and status to technical staff across teams.
• Collaborate with design, verification, and other teams across geographies.

Skills

Self-motivation

Communication

Teamwork

Independent work

Education

Bachelor of Science in Electrical/Computer Engineering or Computer Science

Master of Science in Electrical/Computer Engineering or Computer Science

Tools

SystemVerilog UVM

Python

Cadence tools

CPF/UPF

Job description

Job Title: Lead Verification Engineer

Location: Montreal, Ottawa, Toronto

Overview

This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality. The candidate will primarily be responsible for the verification of digital RTL and development of re‑usable verification components and environments.

It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure. The ideal candidate will have a fundamental understanding of the end‑to‑end verification flow to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status.

The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem‑solving and communication skills. The candidate should be able to work as part of a small and focused team of engineers and be able to collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies.

The candidate should be willing to work full time in the Montreal, Quebec, Canada office and be willing to travel as required by job function (expectation is 5% travel or less). Design IP is a growing organization within Cadence and our complete IP portfolio can be found at http://ip.cadence.com/ipportfolio/ip-portfolio-overview.

Minimum Experience

• Bachelor of Science in Electrical (EE)/Computer Engineering (CPE) or Computer Science (CSC)
• Understanding of verification architecture and methodologies
• Understanding of Metric Driven Verification
• Understanding of Universal Verification Methodologies
• Understanding of the identification, planning and creation of functional coverage and checks
• Understanding of System Verilog Assertions (SVAs)
• Understanding of digital design flow

Preferred Experience

• Master of Science in EE/CPE/CSC
• Experience with SystemVerilog UVM coding language is desired
• Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk is also strongly preferred
• Exposure to standard protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI
• Exposure to formal verification technologies
• Exposure to mixed‑signal design experience
• Experience with Cadence tools
• Exposure to low‑power verification experience using CPF or UPF

Cadence is an equal‑opportunity employer committed to hiring a diverse workforce.

Titre (French)

Localisation: Montreal, Ottawa, Toronto

Cadence Design Systems est à la recherche de candidats d’excellence pour joindre une équipe expérimentée et dynamique d’ingénieurs en charge du développement d’IP au service des standards de l’industrie.

Le candidat sélectionné aura la charge de la vérification de modules numériques RTL et du développement de modules de vérification réutilisables. Le candidat sera aussi amené à contribuer à toutes les phases du processus de vérification : élaboration du plan de vérification, codage des points de couverture, génération de stimuli et analyse de couverture.

Le candidat devra posséder des connaissances de base des méthodes de design et de vérification des composantes numériques. Le candidat devra être autonome, dynamique et démontrer de très bonnes qualités de communication.

Le groupe de design IP est une équipe multidisciplinaire composée d’ingénieurs provenant de divers sites à travers le monde. Faisant partie du groupe de vérification, le candidat sera amené à collaborer avec diverses disciplines et phases de la réalisation complète d’IP matériel : design numérique et analogique, design physique, production, etc.

Expérience Minimum (French)

• Baccalauréat en Ingénierie électrique, sciences appliquées ou domaine connexe.
• Compréhension des principes de base de la vérification de composantes numériques.
• Compréhension de base de la vérification basée sur les métriques (Metric Driven Verification).
• Connaissance des Méthodes de Vérification Universelles (UVM).
• Connaissance du langage d’assertions SystemVerilog (SVAs).
• Compréhension de base du flot de design numérique.
• Capable de communiquer en anglais.

Expérience Recherchée (French)

• Maîtrise en génie électrique, sciences appliquées ou domaine connexe.
• Expérience avec le langage de vérification SystemVerilog UVM.
• Expérience avec différents langages de script tel que Python, Perl, Ruby, etc.
• Connaissance de base des protocoles de transfert de données tel que PCIe, USB, SATA, Ethernet, Display Port, HDMI.
• Connaissance de base des techniques de vérification formelle.
• Connaissance de base des composantes mixtes (analogiques/numériques).

Cadence est une employeuse qui souscrit à l’égalité des chances et qui s’engage à embaucher une main‑d’oeuvre diversifiée.

Compensation et Avantages

The annual salary range for MOUNT‑ROYAL 01 (Montreal) is 89,600.00 – 166,400.00 CAD. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Our benefits programs include: paid vacation and holidays, leave of absence programs, Registered Retirement Savings Plan (RRSP), Tax Free Savings (TFSA) plan for post‑tax investment savings, Employee Stock Purchase Plan, group health coverage that includes dental, vision and Emotional Wellbeing Support (EAP) benefits for you and your eligible dependents. Cadence also offers employee and dependent Life insurance, and short‑term and long‑term disability. In addition, Cadence provides Global Travel Medical coverage, Business Travel Accident Insurance, and a funded Lifestyle Spending Account (LSA).

Additional Information

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We welcome applications from candidates with disabilities and in equity‑seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.