FPGA Development Tools Engineer – Synthesis

191 Altera Corporation; Toronto; On-site; CAD 129,100 - 187,000; Full time

Job summary

191 Altera Corporation is seeking an FPGA Development Tools Engineer in Toronto, Ontario. You will develop and enhance synthesis capabilities to transform RTL designs into optimized hardware implementations. The ideal candidate must have 6+ years of experience in FPGA/ASIC design and strong skills in RTL design.

This position offers a competitive salary range between $129.1K and $187.0K CAD, including performance-based incentives. Join our innovative team and influence the next generation of FPGA technology.

Qualifications

• 6+ years of experience in FPGA/ASIC design or EDA tools.
• Strong hands-on experience with Verilog, SystemVerilog, or VHDL.
• Understanding of logic synthesis and optimization techniques.

Responsibilities

• Design and implement synthesis algorithms for RTL designs.
• Contribute to the FPGA compiler flow integration.
• Analyze synthesis results and drive resolutions.

Skills

RTL design and synthesis

C/C++ for tool development

Algorithms and data structures

Debugging and performance analysis

Education

Bachelor's or Master's degree in relevant field

Tools

Quartus

Vivado

Python

Tcl

Job description

Position Overview

Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our FPGA compiler and development tools are central to enabling customers to efficiently design, optimize, and deploy complex hardware systems on advanced FPGA platforms. The FPGA Development Tools Engineer will join our Synthesis team, focused on advancing the next generation of FPGA compilation technology. In this role, you will develop and enhance synthesis capabilities that transform RTL designs into optimized hardware implementations, directly impacting performance, power, and area (PPA). The ideal candidate brings strong expertise in RTL design and synthesis, combined with a solid software engineering background and a passion for building scalable, high‑performance EDA tools.

Key Responsibilities

• Design, implement, and optimize synthesis algorithms to convert RTL (Verilog/SystemVerilog/VHDL) into efficient gate‑level representations.
• Contribute to the FPGA compiler flow, integrating synthesis with placement, routing, and timing (STA) stages.
• Improve quality of results (QoR) by optimizing performance, power, and area through synthesis‑driven techniques.
• Develop tools and methodologies for analyzing and transforming complex RTL designs.
• Work closely with architecture, STA, placement, routing, and validation teams to ensure alignment across the toolchain.
• Analyze synthesis results, debug issues (timing, logic structure, mapping), and drive resolution.
• Develop internal tools, scripting, and automation to improve synthesis flows and productivity.

Qualifications

• 6+ years of experience in FPGA/ASIC design, EDA tools, or related fields.
• Strong hands‑on experience with Verilog, SystemVerilog, or VHDL RTL design and synthesis flows.
• Proficiency in C/C++ for tool development.
• Strong understanding of algorithms and data structures.
• Familiarity with debugging and performance analysis.
• Understanding of logic synthesis and optimization techniques, FPGA or ASIC design flows (synthesis → P&R → STA), and timing‑driven design considerations.
• Ability to analyze complex systems and develop scalable, high‑performance solutions.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (PhD encouraged).
• Relevant experience gained during doctoral studies may be considered toward the required years of experience.

Preferred Qualifications

• Experience with synthesis tools or FPGA toolchains (e.g., Quartus, Vivado).
• Knowledge of FPGA architectures (LUTs, DSPs, BRAM, interconnect).
• Familiarity with advanced optimizations (retiming, logic restructuring, resource sharing).
• Scripting experience (Python, Tcl).
• Background in compiler development or EDA algorithms.
• Experience working in large, distributed engineering teams.

Why Join Altera

• Build core synthesis technology for next‑generation FPGA platforms.
• Influence compiler architecture and performance at scale.
• Collaborate with world‑class engineers across silicon, architecture, and software.

Job Type

Regular – Shift 1 (Canada)

Primary Location

Toronto, Ontario, Canada (additional locations available)

Estimated Salary Range

$129.1K – $187.0K CAD (base salary plus performance‑based incentives)

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.