FPGA Development Tools Engineer

Altera; Toronto; On-site; CAD 100,000 - 130,000; Full time

Benefits offered by this job

Mentorship and hands-on training from2

Competitive salary and benefits

Opportunities for professional growth

Supportive and innovative work环境

Job summary

Altera in Toronto, Canada, is seeking a senior-level candidate to join the HLS team, developing and maintaining compiler infrastructure that translates C/C++ into hardware descriptions for FPGA/ASIC targets.

The role emphasizes optimizing compiler passes, testing new features, and collaborating across teams to drive performance improvements while leveraging MLIR/LLVM toolchains and HLS tools. Emphasis on AI workloads and hardware acceleration.

Qualifications

• Academic or project experience with C/C++ programming.
• Familiarity with compiler concepts (parsing, code generation, optimization).
• Exposure to digital logic design fundamentals and hardware flows (FPGA/ASIC).
• Familiarity with MLIR, LLVM, or Clang.
• Exposure to HLS tools such as Xilinx Vivado HLS or Intel HLS.
• Basic understanding of hardware description languages (Verilog/VHDL).
• Experience with version control systems (Git).

Responsibilities

• Assist in the development and maintenance of HLS compiler infrastructure.
• Support the implementation of compiler passes and code transformations to optimize high-level code for hardware synthesis.
• Analyze and improve compilation flow from C/C++ to hardware description languages.
• Research in cutting edge compiler technology for AI computation workload.
• Help integrate and test new features in HLS compilers, focusing on performance and resource optimization.
• Participate in debugging and validating compiler outputs.
• Document work and contribute to internal knowledge bases.

Skills

C/C++ programming

compiler concepts

digital logic design

MLIR

LLVM

Clang

Verilog/VHDL

Tools

Git

Xilinx Vivado HLS

Intel HLS

Job description

About Us

Altera is at the forefront of programmable logic and hardware acceleration. Our mission is to empower developers and system architects to rapidly design and deploy cutting-edge solutions using advanced FPGA and SoC technologies. The High Level Synthesis (HLS) team at Altera specializes in creating sophisticated tools and compiler technologies that translate high-level programming languages into efficient hardware implementations. Join us and help shape the future of HLS, enabling faster innovation in fields such as AI, cloud computing, and embedded systems.

Job Details

Job Description:

About Us

Altera is at the forefront of programmable logic and hardware acceleration. Our mission is to empower developers and system architects to rapidly design and deploy cutting-edge solutions using advanced FPGA and SoC technologies. The High Level Synthesis (HLS) team at Altera specializes in creating sophisticated tools and compiler technologies that translate high-level programming languages into efficient hardware implementations. Join us and help shape the future of HLS, enabling faster innovation in fields such as AI, cloud computing, and embedded systems.

Responsibilities

• Assist in the development and maintenance of HLS compiler infrastructure.
• Support the implementation of compiler passes and code transformations to optimize high-level code for hardware synthesis.
• Analyze and improve compilation flow from C/C++ to hardware description languages.
• Research in cutting edge compiler technology for AI computation workload
• Help integrate and test new features in HLS compilers, focusing on performance and resource optimization.
• Participate in debugging and validating compiler outputs.
• Document work and contribute to internal knowledge bases.

What We Offer

• Mentorship and hands-on training from experienced compiler and hardware engineers.
• Competitive salary and benefits.
• Opportunities for professional growth and advancement.
• Supportive and innovative work environment.

Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job‑specific knowledge. In addition to base salary, we offer performance‑based incentive opportunities that reward both individual contributions and overall company success.

Estimated Salary Range: $100,000 - $130,000 CAD

We use artificial intelligence to screen, assess, or select applicants for the position. This posting is for an existing vacancy. Canadian work experience is not required for this role.

Qualifications

Minimum Qualifications

Skills

• Academic or project experience with C/C++ programming.
• Familiarity with compiler concepts (parsing, code generation, optimization) through coursework or personal projects.
• Exposure to digital logic design fundamentals and hardware flows (FPGA/ASIC)

Preferred Qualifications

• Eagerness to learn about HLS compilers and hardware synthesis.
• Good analytical, communication, and teamwork skills.
• Coursework or internship experience in compiler development or hardware synthesis.
• Familiarity with MLIR, LLVM, or Clang.
• Exposure to HLS tools (e.g., Xilinx Vivado HLS, Intel HLS).
• Basic understanding of hardware description languages (Verilog/VHDL).
• Experience with version control systems (e.g., Git).

Job Type

Regular

Shift

Shift 1 (Canada)

Primary Location:

Toronto, Ontario, Canada

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.