Engineer, Staff Analog Design Ottawa

SiTime Corp.; Ottawa; In loco; CAD 110.000 - 150.000; Tempo pieno

Vantaggi offerti da questo lavoro

Equity grants

Quarterly bonus

Competitive compensation

Descrizione del lavoro

SiTime Corp. is seeking a Staff Analog Design Engineer to lead the development of high-performance timing products from specification through silicon. You will work with product teams and support validation, qualification, and new product releases in Ottawa, Canada.

The role requires a Master’s or PhD in EE with 6+ years of analog/mixed-signal IC design experience, proficiency in CMOS/BiCMOS, and strong Cadence tool expertise. Collaboration with cross-functional teams is essential for success.

Competenze

• Master’s or PhD in Electrical Engineering.
• 6+ years analog/mixed-signal IC design experience.
• Proven CMOS/BiCMOS IC design experience.
• Experience with PLLs or related blocks (VCOs, phase detectors, charge pumps).
• Strong knowledge of transistor behavior and noise concepts.
• Cadence analog/mixed-signal simulation tools familiarity.
• Analog/mixed-signal design flow and post-layout verification knowledge.
• Experience with SystemVerilog/Verilog-A/AMS.
• Hands-on lab test and characterization experience.

Mansioni

• Design analog circuits for high-performance timing products.
• Incorporate circuit blocks into complete chip designs.
• Collaborate with cross-functional teams (layout, digital, system design, validation).
• Test, debug, and characterize lab prototypes.
• Support product validation and customer applications.

Conoscenze

Analog IC design

PLL design

Cadence tools

SystemVerilog/Verilog-A

Formazione

Master’s degree in Electrical Engineering

PhD in Electrical Engineering

Strumenti

Cadence software

AMS

Verilog-A

Verilog

Descrizione del lavoro

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com .

Job Summary

SiTime is looking for a Staff Analog Design Engineer to join a talented analog design team developing advanced clock and timing products. You will lead the development of key circuit blocks from specification through proven silicon. This role requires a solid understanding of top-level architecture and system-level requirements. You will collaborate closely with product development teams and support validation, qualification, and new product release.

Responsibilities:

• Develop specifications and design analog circuits for high-performance timing products
• Incorporate circuit blocks into the complete chip design
• Collaborate with distributed cross-functional teams, including layout, digital, system design, and validation
• Test, debug, and characterize lab prototypes
• Support product validation and customer applications

Qualifications & Requirements:

• Master’s or PhD degree in Electrical Engineering.
• 6+ years of relevant analog/mixed-signal IC design experience.
• Proven experience in CMOS and/or BiCMOS IC design.
• Strong knowledge of integrated circuit design, device physics, and advanced process technologies
• Experience designing PLLs or related blocks such as VCOs, phase detectors, charge pumps, and supporting circuits
• Solid understanding of transistor behavior, circuit noise theory, and phase-noise concepts
• Proficiency with the Cadence analog/mixed-signal simulation toolset
• Familiarity with analog/mixed-signal design flow, simulation methods, design rules and post-layout verification
• Experience with analog behavioral modeling, SystemVerilog, Verilog-A, and AMS
• Hands-on lab test and characterization experience

It is not necessary to meet all job requirements to be a qualified candidate for the position.

Desired Characteristics & Attributes:

• Collaborative, self-motivated, and positive team contributor
• Able to empower others and provide effective mentorship
• Strong analytical and problem-solving skills

Compensation:

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.

In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law.

Learn More about SiTime:

Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.