Engineer II-Emulation

FHLB Des Moines

Burnaby

Hybrid

CAD 106,000 - 159,000

Full time

14 days+
Application generator

Get a reply from this employer — a resume and cover letter tailored to exactly what they’re hiring for.

Get past ATS filters

Benefits offered by this job

Health benefits from day one
Retirement savings plans
IESPP program (6‑month look back)

Job summary

Microchip Technology Inc. seeks an Architecture Co-Verification Engineer to join the ACOV team, enabling HW/FW development and co-verification of state-of-the-art SoCs using Cadence Palladium emulators and Cadence Protium prototyping platforms.

You will work with architects, hardware designers, firmware and verification teams throughout the SoC development cycle. This high-visibility role develops broad skills and problem-solving abilities in a global organization.

Qualifications

  • BS/MS in Electrical/Electronic Engineering, Computer Science, or Computer Engineering.
  • 2 years or less of relevant work experience with Master's degree; strong analytical and documentation skills.
  • Familiarity with Linux, programming in Python/Tcl/C; problem-solving and team collaboration required.

Responsibilities

  • Enable HW/FW development and co-verification for SoCs using emulators and FPGA platforms.
  • Collaborate with architects, hardware designers, firmware engineers, and verification teams.
  • Contribute to pre/post-silicon verification, testing, and debug activities.

Skills

Python
C
Linux
Tcl
RTL design
MIPS/ARM/RISC‑V
PCIe
Git/Subversion
FPGA/Emulation

Education

BS/MS in Electrical/Electronic Engineering, Computer Science, or Computer Engineering

Tools

Cadence Palladium
Cadence Protium
Git
Subversion

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Job Description

The ArchitectureCo-Verification team (ACOV) is an exciting, fast-paced team responsible for enabling HW/FW development and co-verification of state‑of‑art System‑On‑Chip (SoC) devices using industry-leading HW emulators (such as Cadence Palladium) and FPGA based prototyping platforms (such as Cadence Protium). The team is deployed in all aspects of SoC development phases from architectural exploration to post‑silicon validation, HW/FW co-development, pre‑silicon functional co‑verification, pre/post‑silicon performance testing, power analysis, and critical post‑silicon investigations. As an emulation Engineer, you will be working closely with architects, hardware designers, firmware engineers, and verification teams throughout the SoC development process. This is a role for a versatile engineer that enjoys the challenges of HW/FW co‑development and system‑level co‑verification using leading‑edge HW emulators and FPGA platforms. It’s a high‑visibility role that will develop a wide range of skills and exceptional problem‑solving abilities.

Requirements/Qualifications
  • BS/MS in Electrical/Electronic Engineering, Computer Science, or Computer Engineering.
  • Minimum two years or less of relevant work experience with Master's degree Excellent analytical and documentation skills.
  • Strong problem solving, communication and interpersonal skills are required.
  • Willing to learn in a fast‑paced environment, being a self‑starter, and organized.
  • LINUX experience and strong programming and scripting skills with languages such as Python, Tcl, and C.
  • Highly motivated team player who sets personal goals and achieves those goals with minimal supervision.
  • Familiarity in C/C++ embedded FW development.
  • Understanding of digital design, RTL coding, simulation and debug.
  • Knowledge of MIPS, ARM and RISC‑V CPUs architecture.
  • Experience troubleshooting server system hardware and networking infrastructure to root cause issues.
  • Desirable: Experience with validation or verification of protocols such as PCIe, CXL, SAS/SATA and NVMe.
  • Experience in memory technologies like DDR4/DDR5.
  • Familiarity in C/C++ embedded FW development.
  • Understanding of digital design, RTL coding, simulation and debug.
  • Knowledge of MIPS, ARM and RISC‑V CPUs architecture.
  • Experience troubleshooting server system hardware and networking infrastructure to root cause issues.
  • Familiarity with Front‑End design and implementation.
  • Knowledge of source control systems such as subversion and/or Git.
  • Experience with FPGA‑based Verification/emulation.
  • Experience with Computer System I/O hierarchies and interconnects (I2C, SPI/ eJTAG), specifically with PCIe protocols and infrastructure.
  • Experience with test automation, testing methodologies, and test tools.
  • Experience working in Linux and Windows Environments and file system structure.
Travel Time

Travel Time: 0% - 25%

Benefits of working at Microchip
  • The annual base salary range for this position is $76,000-$114,000.* *Range is dependent on numerous factors including job location, skills and experience.
  • Health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature.
Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Engineer II-Emulation
Engineer II-Emulation

Microchip Technology Inc. • Burnaby

On-site
CAD 105,000 - 158,000
Health benefits day one
Competitive compensation
Engineer II - Validation (Systems)
Engineer II - Validation (Systems)

FHLB Des Moines • Burnaby

On-site
CAD 105,000 - 157,000
Health benefits from day one
Retirement savings plans
RSUs and quarterly bonus
+1
Technical Staff Engineer-Firmware
Technical Staff Engineer-Firmware

FHLB Des Moines • Burnaby

On-site
CAD 148,000 - 313,000
Competitive base pay
Restricted stock units
Quarterly bonus payments
+3
Engineer II - Validation (Systems)
Engineer II - Validation (Systems)

Microchip Technology Inc. • Burnaby

On-site
CAD 105,000 - 158,000
Principal Engineer-Firmware
Principal Engineer-Firmware

Microchip Technology Inc. • Burnaby

On-site
CAD 122,000 - 263,000
Health benefits day one
Retirement savings plans
IESPP program
Technical Staff Engineer-Firmware
Technical Staff Engineer-Firmware

Microchip Technology Inc. • Burnaby

On-site
CAD 148,000 - 313,000
Health benefits from day one
Quarterly bonus payments
Restricted stock units
Technical Staff Engineer - Design
Technical Staff Engineer - Design

FHLB Des Moines • Burnaby

On-site
CAD 149,000 - 314,000
Health benefits that begin day one
Retirement savings plans
Restricted stock units
+1
ASIC Development Engineer
ASIC Development Engineer

FHLB Des Moines • Burnaby

Hybrid
CAD 106,000 - 159,000
Health benefits from day one
Retirement savings plan
Quarterly bonus payments
+1
Senior Software Architect - RISC-V Embedded Systems
Senior Software Architect - RISC-V Embedded Systems

FHLB Des Moines • Burnaby

On-site
CAD 151,000 - 319,000
Health benefits from day one
RSUs (restricted stock units)
Quarterly bonus payments
+1
Principal Engineer-Firmware
Principal Engineer-Firmware

FHLB Des Moines • Burnaby

On-site
CAD 86,000 - 186,000
Health benefits from day one
Quarterly bonus payments
Restricted stock units (RSUs)