Emulation Build Architect

Bilinguallink; Banff; On-site; CAD 90,000 - 130,000; Full time

Job summary

Bilinguallink seeks an Emulation Build Engineer to own end-to-end RTL-to-emulation model builds for high‑fidelity hardware emulation platforms. You will bridge RTL design teams with validation/software, enabling early firmware development and co‑verification across Palladium/Protium/ZeBu platforms.

Responsibilities include building and optimizing emulation flows, resolving synthesis issues, and maintaining automated pipelines. Strong RTL, scripting, and memory/clock modeling skills are essential.

Qualifications

• Education: B.S./M.S. in Electrical Engineering, Computer Engineering, or related field
• Experience: 3–8+ years in emulation model build, FPGA prototyping, or related hardware compilation roles
• Hands-on with emulation/prototyping platforms (Palladium/Protium/ZeBu)
• Strong RTL design constructs and synthesizability (Verilog/SystemVerilog)
• Experience with logic synthesis concepts (mapping, optimization, timing constraints)
• Proficiency in scripting and automation: Python, Perl, Tcl, Bash, Makefiles
• Memory modeling knowledge (SRAM/ROM/FIFO wrappers) and abstraction
• Clock modeling strategies in emulation
• Understanding design hierarchy, IP integration, SoC-level build complexity
• Version control (Git/Perforce) and build management systems

Responsibilities

• Emulation Model Build & Compilation: build, compile, and optimize RTL-to-gate/behavioral models for Palladium/Protium/ZeBu
• Own the emulation build flow from RTL ingestion through synthesis, partitioning, mapping, place-and-route, bitstream generation
• Resolve synthesis/compilation errors including unresolved modules, black-box instantiation, clock/reset inference
• Maintain RTL waivers and design abstraction to achieve clean compilations
• Optimize build configurations for compile time, resource usage, emulation speed, capacity
• Manage incremental/hierarchical build strategies to reduce turnaround time
• Support multi-domain/multi-clock designs with proper clock modeling

Skills

RTL design

Verilog/SystemVerilog

Python scripting

FPGA prototyping

CI/CD automation

Git/Perforce

Clock modeling

Memory modeling

Build optimization

Debug emulation

Education

B.S./M.S. in Electrical Engineering or Computer Engineering

Tools

Cadence Palladium

Cadence Protium

Synopsys ZeBu

LSF

SGE

Slurm

Job description

Bilinguallink seeks an Emulation Build Engineer to own end-to-end RTL-to-emulation model builds for high‑fidelity hardware emulation platforms. You will bridge RTL design teams with validation/software, enabling early firmware development and co‑verification across Palladium/Protium/ZeBu platforms.

Responsibilities include building and optimizing emulation flows, resolving synthesis issues, and maintaining automated pipelines. Strong RTL, scripting, and memory/clock modeling skills are essential.