Principal Physical Design and Integration Engineer

Marvell Semiconductor, Inc.; Morrisville; On-site; USD 148,000 - 220,000; Full time

Job summary

A leading semiconductor company is seeking a Principal Physical Design and Integration Lead to join their Data Center Engineering team. This role involves leading complex chip designs, ensuring performance and power requirements are met, and mentoring a team of engineers. The ideal candidate will have extensive experience in physical design and a strong background in leading teams. This is an onsite position located in Morrisville, NC, offering competitive compensation and benefits.

Benefits

Flexible time off

401k

Year-end shutdown

Floating holidays

Paid time off to volunteer

Qualifications

• 10+ years of experience in physical design or 5+ years with MS.
• Experience leading a team at the chip/sub-system level.
• Knowledge of Verilog/VHDL and digital logic.

Responsibilities

• Lead design phases for complex chip/sub-system.
• Coordinate with various teams for subsystem integration.
• Debug timing and routing issues across hierarchical levels.

Skills

Leadership

Communication

Detail-oriented

Education

BS in EE/CE/CS

MS in EE/CE/CS

Tools

Cadence Innovus

Siemens Calibre

Synopsys ICV

Cadence Voltus

Perl

Python

TCL

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Data Center Engineering (DCE) Physical Design team at Marvell is seeking candidates for a Principal Physical Design and Integration Lead engineering position. Projects within DCE range from artificial intelligence and machine learning to wired and wireless infrastructure, with the latest technology nodes. The team utilizes the latest EDA software tools and works through the technical challenges to ensure we meet the performance, power, and area requirements of the design. This position will work in tandem with the other Physical Design related teams, such as Timing, Physical Verification, Power Integrity and other teams both at a local and global level.
This work role will be located in Morrisville, NC.

What You Can Expect

• In this onsite role at the Morrisville site, you will be the leader on a large complex chip/sub-system/partition through all phases of the design
• Responsible for floorplanning a chip/sub-system/partition, pushing down block boundary and pin assignment to team members
• Work with a variety of teams to pull in their required portion of the sub-system, such as DFT and clock distribution teams
• Leading a small group of engineers at the block level, ensuring they are progressing, meeting milestones on schedule and quality, and correct deliverables

• Work closely with the block level PD engineers in debugging and resolving timing and routing issues across all hierarchical levels

• Be an active team member on physical design methodology
• Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes

• Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation

What We're Looking For

Minimum Qualifications

• BS in EE/CE/CS with 10+ years of experience, or MS in EE/CE/CS with 5+ years of experience
• 5 years of practical experience in physical design at all levels of hierarchy with multiple ASICs/SOCs
• Physical design knowledge and experience, from RTL or netlist handoff to GDS tape-out
• Extensive experience with floorplanning at a sub-system/partition level, considering boundary snap of power/technology and pin assignment
• Proficient in running chip/sub-system/partition level signoff, including physical verification (DRC and LVS), along with power integrity (EMIR)
• Experienced in leading a team of block-level engineers, coordinating at the sub-system/partition level
• Good knowledge of Verilog/VHDL, and track record of collaboration with RTL team
• Good understanding of digital logic and architecture
• Proficient in LINUX and shell-based scripting
• Knowledge and experience with TCL language
• Diligent, detail-oriented, and able to handle assignments with minimal supervision
• Must possess good communication skills, be a self-driven individual, and a good team player

Preferred Qualifications (in addition to the minimum qualifications)

• BS in EE/CE/CS with 15+ years of experience, or MS in EE/CE/CS with 10+ years of experience
• 10 years of practical experience as a leader of a team at the chip/sub-system/partition level for multiple ASICs/SOCs
• Worked with timing and clock teams on planning and integration of high-speed clock distribution
• 5nm/3nm experience with chip-level floorplanning, including bump/UBM, MIMCAP insertion, AP routing, and DFM planning.
• Floorplanning and Physical Design with Cadence Innovus
• Physical Verification with Siemens Calibre and/or Synopsys ICV
• Power Integrity Signoff with Cadence Voltus
• Peripheral IO Pad assignment and associated RDL
• Bump assignment planning and collaboration with fullchip and package team
• Experience with Analog IP integration and implementation
• Knowledge and experience with Python language
• Experience with low-power design methodology and implementation
• Have led or participated in Physical Design and Integration methodology

Expected Base Pay Range (USD)

148,500 - 219,780, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [e-mail].

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