Design Verification Engineer

LanceSoft, Inc.; Ottawa; On-site; Full time

Job summary

A leading company in the semiconductor industry is seeking a Design Verification Engineer in Ottawa. The ideal candidate will have a strong background in processor architecture and verification, along with excellent communication skills. This role offers the opportunity to contribute to innovative technologies and support career development in a collaborative environment.

Qualifications

• 5+ years of experience in design verification.
• Proficiency in SystemVerilog and UVM.
• Strong analytical and problem-solving skills.

Responsibilities

• Develop and maintain tests for functional verification with UVM.
• Build testbench components for next-generation IP.
• Provide technical support to other teams.

Skills

UVM

SystemVerilog

C

C++

Education

Bachelor's degree in Computer or Electrical Engineering

Tools

Perl

Ruby

Makefile

Job description

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This range is provided by LanceSoft, Inc.. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$80.00/hr - $92.00/hr

Direct message the job poster from LanceSoft, Inc.

(US/Canada Staffing) Semiconductor / VLSI / EDA / Embedded

Pay Rate- $80 - $92 hourly on T4

Job Description

THE ROLE:

We are looking for an adaptive, self-motivated design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve CLIENT's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team fosters continuous technical innovation and supports career development.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification. You are a team player with excellent communication skills and experience collaborating across different sites and time zones. You possess strong analytical and problem-solving skills, and are eager to learn and tackle new challenges.

KEY RESPONSIBILITIES:

• Develop and maintain tests for functional verification with UVM at the subsystem level
• Build testbench components for next-generation IP
• Maintain or improve current test libraries for IP level testing
• Lead IPs in Control Fabric technically
• Gain exposure to AXI protocol and Bootcode Verification
• Provide technical support to other teams

TOP PRIORITY SKILLS:

UVM, SystemVerilog, C, C++

PREFERRED EXPERIENCE:

• 5+ years of experience
• Proficiency in SystemVerilog and UVM
• Scripting skills in Perl, Ruby, and Makefile
• Familiarity with SystemVerilog and modern verification libraries

ACADEMIC CREDENTIALS:

Bachelor's (required) or Master's degree in Computer or Electrical Engineering

Seniority level

Mid-Senior level

Employment type

Contract

Job function

Semiconductor Manufacturing

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