DDR Subsystem Architect

Arm; Old Toronto; On-site; USD 180,000 - 245,000; Full time

Job summary

An established industry player is seeking a skilled DDR Subsystem Architect to lead the hardware architecture for advanced memory subsystems. This pivotal role involves collaborating with SoC architects and vendors to define subsystem requirements, author specifications, and ensure high-performance silicon production. With a focus on innovative solutions across various sectors including mobile and automotive, this position offers a unique opportunity to contribute to cutting-edge technology. Join a dynamic team that values creativity and expertise, and be part of a company dedicated to excellence and equity in the workplace.

Qualifications

• 10+ years of experience in a senior development position.
• Deep understanding of DDR controller design and memory types.

Responsibilities

• Create product intercept roadmaps using JEDEC specs and vendor roadmaps.
• Draft architectural specifications for design and implementation teams.

Skills

DDR controller design

Memory types (LPDDR, DDR, HBM, GDDR)

Controller-to-PHY interface protocols (DFI)

Arm bus protocols (APB, AXI, CHI, CXS)

Performance/QoS, RAS, security, power-management

Debug and test features

Excellent communication skills

Education

Bachelor's degree in Electrical Engineering

Master’s degree in Electrical Engineering

Job description

Job Overview:

DDR Subsystem Architect is a technical role responsible for hardware architecture of LPDDR, DDR, HBM and GDDR subsystems for high-volume, sophisticated, SoC platforms on groundbreaking process nodes across multiple market segments including mobile, automotive, datacenter and networking, and IoT.

This position plays a meaningful role in the development of production-quality silicon with outstanding performance and power efficiency, both in partnership with Arm partners and producing Arm development silicon.

Responsibilities:

• Consume JEDEC specs and DRAM vendor roadmaps to create product intercept roadmaps.
• Work with SoC architects, business-units, and customers to establish & reconcile DDR subsystem features & requirements.
• Author architectural specifications to a mature stage allowing design and implementation teams to engage actively.
• Work with IP vendors to draft, negotiate, and execute SoWs/contracts.
• Work with design, verification, and validation teams to draft and review design specifications & test-plans (pre & post silicon), and support execution teams as required.
• Debug performance and functional issues with high-level models, RTL simulation, hard and soft IP.

Required Skills and Experience:

• Deep understanding of DDR controller design and memory types (LPDDR, DDR, HBM, GDDR).
• Experience with controller-to-PHY interface protocols (DFI).
• Familiarity with Arm bus protocols such as APB, AXI, CHI, CXS, etc.
• Experience with performance/QoS, RAS, security, power-management, debug, and test features in the context of DDR subsystems.
• Bachelor's or Master’s degree in Electrical or Computer Engineering with minimum 10 years of experience in a senior development position.
• Excellent presentation, interpersonal, written, and verbal communication skills.

Salary Range:

$180,922-$244,777 per year. We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process.

Equal Opportunities at Arm:

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.