ASIC Physical Designer

Talentlab; Toronto; On-site; CAD 80,000 - 120,000; Full time

Job summary

A specialized semiconductor technology firm is seeking a Physical Design Engineer to join their dynamic team in Toronto. This role focuses on executing critical physical design tasks, ensuring layout verification, and enhancing technology nodes. Candidates should have strong expertise in physical design methodologies and relevant CAD tools, embedded in a fast-paced environment alongside industry experts.

Qualifications

• Experience with physical design CAD flows and design verification.
• Proficiency in DRC, LVS, and debug methodologies.
• Hands-on experience with Cadence Virtuoso preferred.

Responsibilities

• Assist Design Engineering (DE) Leads in executing physical design, including Performance Verification.
• Perform layout verification and reliability checks.

Skills

Physical design CAD flows

Design verification

DRC

LVS

Scripting skills in PERL

Scripting skills in Shell

Communication skills

Team collaboration

Education

Bachelor’s degree (BS+) in a relevant field

Tools

Cadence Virtuoso

Unix/Linux environments

Job description

Physical Design Engineer

About the Team:
Our client, a global leader in semiconductor innovation, is looking for a Physical Design Engineer to join their high-performing team in North York, Ontario. This team plays a critical role in executing physical design tasks and ensuring high-quality layout verification and reliability checks. If you're looking for an opportunity to collaborate with industry-leading experts in a dynamic, fast-paced environment, this role is for you.

What Our Client Offers:

• A fast-paced, dynamic environment working on advanced technology nodes.

• An opportunity to work alongside top industry professionals in semiconductor design.

• The ability to make a meaningful impact on next-generation semiconductor technology.

Key Responsibilities:

• Assist Design Engineering (DE) Leads in executing physical design, including Performance Verification.

• Perform layout verification and reliability checks.

Required Skills:

• Experience with physical design CAD flows and design verification.

• Proficiency in DRC, LVS, and debug methodologies.

Preferred Skills:

• Hands-on experience with Cadence Virtuoso.

• Scripting skills in PERL and Shell for automation and workflow efficiency.

• Familiarity with Unix/Linux environments.

• Strong communication and team collaboration skills.

• Bachelor’s degree (BS+) in a relevant field.

• Preferred experience in Process node design.

This is an exciting opportunity to work on cutting-edge semiconductor technology and be part of a team that is shaping the future of high-performance computing. If you have the required skills and experience, please reach out to [e-mail]