ASIC Engineer Intern

Ciena; Ottawa; On-site; CAD 35,000 - 48,000; Full time

Benefits offered by this job

Employee Assistance Program

Company-paid holidays

Paid sick leave

Vacation pay

Job summary

Ciena is seeking a student for a 4- to 8-month term starting January 2027 to contribute to automation infrastructure for ASIC devices.

You will collaborate with developers and team leads to advance ASIC design, layout, integration, and verification, develop design blocks, and implement netlists into layouts while enhancing Python-based workflows. The role emphasizes learning in a fast-paced, collaborative environment.

Qualifications

• Experience programming in Java, Python, TCL, or SystemVerilog.
• Familiarity with Linux-based development environments.
• Experience with ASIC/FPGA development is a plus.

Responsibilities

• Contribute to the development of automation infrastructure for ASIC devices.
• Collaborate with developers and team leads to advance ASIC design, layout, integration, and verification activities.
• Develop design blocks and evaluate designs for correctness and performance.
• Implement netlists into silicon-realizable layouts and automate placement and extraction workflows.
• Create constraints, analyze implementation reports, and automate ASIC integration processes.
• Develop reusable SystemVerilog/UVM verification components.
• Enhance Python-based reporting, analysis, build, simulation, and debug workflows.

Skills

SystemVerilog

Python

Java

TCL

Skill/Ocean

Linux

Tools

JIRA

Confluence

Git

Job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.

Opportunity

Work term of 4 months extendable to 8, starting in January 2027.

How You Will Make An Impact

• Contribute to the development of automation infrastructure for ASIC devices.
• Collaborate with developers and team leads to advance ASIC design, layout, integration, and verification activities.
• Develop design blocks and evaluate designs for correctness and performance.
• Implement netlists into silicon-realizable layouts and automate placement and extraction workflows.
• Create constraints, analyze implementation reports, and automate ASIC integration processes.
• Develop reusable SystemVerilog/UVM verification components.
• Enhance Python-based reporting, analysis, build, simulation, and debug workflows.

Must Haves

• Programming experience using one or more of Java, Python, TCL, Skill/Ocean, or SystemVerilog.
• Familiarity with Linux-based development environments.

Nice To Haves

• Previous experience with ASIC or FPGA development programs.
• Strong analytical and debugging skills.
• Familiarity with Agile, JIRA, Confluence, and Git.

Pay Range

The hourly pay range for this position is $25.50 - $35.00.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.