ASIC Digital Verification Engineer – Mixed-Signal Timing

SiTime; Ottawa; On-site; CAD 76,000 - 104,000; Full time

Benefits offered by this job

Quarterly bonus

Equity grants

Job summary

SiTime in Ottawa is seeking a talented Digital Verification Engineer to join our team. You will work on mixed-signal digital PLL ICs, contributing to testcase development, verification planning, and ongoing improvements of the verification environment.

You will participate in a growing team, collaborating with design and verification colleagues across locations to ensure verification closure and high-quality silicon.

Qualifications

• Experience with SystemVerilog and UVM verification environments.
• Proficiency with Synopsys and Cadence simulation tools.
• Unix/Linux operating system experience.
• Strong communication and teamwork abilities.

Responsibilities

• Define and implement self-checking test cases from functional specs.
• Contribute to verification infrastructure components.
• Triage regressions, debug RTL and gate-level sims, analyze coverage.
• Collaborate with diverse, local and remote team members.

Skills

SystemVerilog

UVM environments

Unix/Linux

Communication skills

Education

Bachelor’s degree in Electrical Engineering

Tools

Synopsys tools

Cadence tools

Job description

SiTime in Ottawa is seeking a talented Digital Verification Engineer to join our team. You will work on mixed-signal digital PLL ICs, contributing to testcase development, verification planning, and ongoing improvements of the verification environment.

You will participate in a growing team, collaborating with design and verification colleagues across locations to ensure verification closure and high-quality silicon.