ASIC Digital Design Verification - Principal Engineer

Synopsys, Inc.; Eastern Ontario; On-site; CAD 80,000 - 100,000; Full time

Job summary

An established industry player is seeking a Principal Engineer for ASIC Digital Design Verification. This role involves joining the Functional Verification team and contributing to the development of cutting-edge Security IP cores. You will be responsible for creating verification strategies and environments, implementing simulations, and collaborating with design engineers to ensure the highest security standards in silicon design. If you are passionate about digital hardware verification and eager to tackle challenging projects in a dynamic environment, this opportunity is perfect for you. Join a team that values innovation and excellence in a field that is increasingly vital in today's technology landscape.

Qualifications

• Hands-on verification experience with digital hardware is essential.
• Strong knowledge of SystemVerilog and UVM is required.

Responsibilities

• Join the Functional Verification team for Security IP cores.
• Develop verification strategies and create functional verification environments.

Skills

SystemVerilog

UVM

Constrained-Random Verification

Coverage-Directed Verification

Python

Linux Shell Scripting

Problem Solving

Communication Skills

Interpersonal Skills

Education

Bachelor's in Computer/Electrical Engineering

Master's in Computer/Electrical Engineering

Bachelor's in Computer Science

Master's in Computer Science

Tools

Verification Methodology

Simulation Tools

Job description

ASIC Digital Design Verification - Principal Engineer

Synopsys is a worldwide leading supplier of semiconductor IP, which is used by our customers to design semiconductor integrated circuits. The product portfolio includes IP components and subsystems for Security, USB, DDR, PCIe/CXL, CPU cores, processor peripherals, embedded memories and much more.

For the Security IP hardware team, we are looking for a Digital Verification Engineer who will join in the development of digital IP cores and subsystems to extend our portfolio for Security IP. This is an extremely challenging and exciting position in an era where (the lack of) embedded system security is frequently causing headlines in the global news. The Synopsys Security IP is targeting the most efficient silicon design solutions with the highest level of security. We are looking to fill this position in the Synopsys office in Kanata (Ottawa) Canada.

Key Responsibilities

• Join the Functional Verification team of Security IP cores and subsystems
• Contribute to developing verification strategies and verification plans
• Contribute to creating state-of-the-art functional verification environments
• Contribute to implementation, development, and automation of simulations and regressions
• Generate verification reports and provide status updates during product development
• Collaborate with peer design and verification engineers on debug and bug fixes
• Stay up to date on state-of-the-art verification methodology and tools

Requirements

• Bachelors or Masters, in Computer/Electrical Engineering or Computer Science
• Experience in and enthusiasm for hands-on verification of digital hardware
• Knowledge of and experience with SystemVerilog and UVM
• Knowledge of and experience with Constrained-Random and Coverage-Directed verification
• Knowledge of and experience with scripting, including Python and Linux shell
• Excellent problem solving and debugging skills
• Excellent communication skills, both written and verbal
• Excellent interpersonal and collaboration skills within a team environment

If you’ve read through the job description and are passionate about verification and this opportunity, please reach out to us telling us why!