ASIC Digital Design, Engineer

Synopsys, Inc.; Mississauga; On-site; CAD 70,000 - 90,000; Full time

Job summary

A leading technology company is seeking a motivated individual to join their PHY Digital Design Verification team. The role involves verifying cutting-edge PCIe and USB designs while working alongside skilled engineers. Candidates with a BS/MS in Computer Engineering and a passion for innovation are encouraged to apply for this exciting opportunity to contribute to advanced chip design technologies.

Qualifications

• Less than 2 years of experience in digital design or verification positions.
• Experience writing test cases in Verilog and System Verilog.
• Ability to debug complex testbench and design-related issues.

Responsibilities

• Defining and tracking Verification Testplans.
• Designing and writing SystemVerilog testbenches using UVM.
• Debugging RTL and gate-level simulation failures.

Skills

Digital Circuit Design

Python

Perl

Testbench Debugging

SystemVerilog

Verification Methodology

Education

BS/MS in Computer Engineering or related fields

Tools

Jira

Job description

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Seeking a highly motivated individual to join our PHY Digital Design Verification team based in Mississauga, Canada. The candidate will be involved in verifying current and next generation PCIe, USB 3/4, and/or MIPI CPHY/DPHY SERDES products. The position offers an excellent opportunity to work with digital and mixed signal design engineers accountable for delivering high-end mixed-signal designs.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Responsibilities:

• Defining and tracking Verification Testplans
• Designing and writing constrained-random SystemVerilog testbenches using a Verification Methodology such as UVM (Universal Verification Methodology)
• Creating and examining Functional Coverage
• Writing SystemVerilog assertions
• Debugging RTL and gate-level simulation failures
• Firmware Debug
• Bug Tracking using Software Tools such as Jira
• Code Coverage Analysis

Skills required:

• BS/MS in Computer Engineering or related fields with <2 years of experience in digital design or verification positions
• Experience in writing testcases in Verilog and System Verilog
• Experience in debugging complex testbench and design related issues
• Solid understanding of digital circuit design
• Familiarity with scripting languages (Python or Perl)
• Self-learner, independent, good organization and communication skills